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1.
被动测试和主动测试的研究   总被引:4,自引:1,他引:4  
协议测试对于保证协议实现的正确性起着至关重要的作用.现在研究较多的测试方法是主动测试,被动测试则是一种新兴的测试方法.对两种测试思想进行比较,提出了将两者结合以获得更好测试质量和测试效率的算法,即先对IUT进行被动测试.通过测试收集一些有用的启发式信息.然后再将这些信息用于指导后续的主动测试,此算法已被用于BGP协议的测试,实验证明该算法可以提高主动测试效率。  相似文献   

2.
征兆测试和奇偶测试是已经使用多年的基于穷尽输入的固定型故障测试方法.在征兆测试与奇偶测试相结合的基础上,提出了一种新的征兆测试方法,即三阶征兆测试法.本方法的特点在于提高测试效率的同时也提高了征兆测试的故障覆盖率,使得原来征兆不可测的电路也可以进行征兆测试.其主要思想是在传统征兆测试的基础上首先引进奇偶测试,对被测电路进行预处理,提高测试效率;然后,对征兆测试作进一步升华处理,成为二阶、三阶征兆测试,提高测试的故障覆盖率.通过对部分基准电路和常用电路的测试实验验证了所提新方法的实用性和有效性.  相似文献   

3.
蔡烁  邝继顺  崔昌明 《微处理机》2007,28(3):14-17,20
瞬态电流测试(IDDT Testing)作为传统电压测试和稳态电流测试(IDDQ Testing)方法的一个补充,越来越受到研究领域和工业界的关注。针对不同的故障类型,基于瞬态电流测试的测试方法也有所不同。这里提出了一种关于时延故障的测试产生算法,该算法利用3个向量来激活时延故障。实验结果表明该测试产生算法用于检测时延故障是可行的。  相似文献   

4.
伪随机测试在数字系统的故障测试中已经得到了多年的应用,但传统的伪随机测试存在着效率比较低的缺陷。针对该缺陷提出了在伪随机测试方法中引入测试码之间距离的概念。根据测试码之间距离越大,能检测到不同故障的数目概率也越大的假设,基于测试码之间距离的随机测试法(简称基于距离测试法)可以生成一组测试码序列。但是由于基于距离测试法所生成的测试码相邻间距离的变大,将造成相邻输入码之间的跳变次数增多,使得输入测试码时所需要的功耗急剧增大。针对该情况,提出对伪随机测试法生成的测试码输入顺序进行重新排序和调整的概念,从而达到降低测试功耗的最终目标。  相似文献   

5.
浦云明 《计算机应用》2008,28(4):1023-1025
分析了结构性测试和功能性测试方法及其优劣,提出了一种平衡结构性测试和功能性测试的模型方法,即定义-使用测试方法。该方法定义了介于全路径指标和全边之间的测试覆盖指标,提供了一种检查缺陷可能发生点的系统化方法。模拟实例结果表明,定义-使用测试方法能够显著提高发现缺陷的效率。  相似文献   

6.
路径测试中基本路径集的自动生成   总被引:1,自引:0,他引:1       下载免费PDF全文
路径测试是一种重要的白盒测试技术,具有较高的故障覆盖率。基本路径集覆盖了程序中所有语句和分支,该文测试了基本路径集中的路径,在测试资源有限的情况下得到较好的测试效果,并提出了基于图的深度优先搜索的基本路径集的生成方法,该算法采用的生成子路径的方法可以有效地减少路径生成过程中的搜索过程,提高路径生成的效率。 关键词:  相似文献   

7.
在分布式应用中,系统配置项多,系统集成测试比较复杂。针对上述情况,提出分布式应用的系统协同测试方案,给出应用场景分析过程、测试脚本文件生成方法及分布式系统性能、功能和接口协同测试的实现,在此基础上对分布式系统进行故障检测和质量评估。实践结果证明了该协同测试方案在提高测试效率、节约测试成本方面的有效性。  相似文献   

8.
组合电路随机测试的一种新方法   总被引:1,自引:0,他引:1       下载免费PDF全文
本文在随机测试的基础上提出了逆随机测试(ART)的新概念,在该测试序列的集合中各测试码之间的海明距离为尽可能的大,这样可以使不同的测试码检测到更多不同的故障,从则提高了测试效率和故障覆盖率。本文给出了构造逆随机测试序列(ARTS)的详细过程,并且严格证明了该序列的高效和正确性,同时还给出了用Benchmark和其它电路作为例子的实验结果。  相似文献   

9.
刘积仁  都军 《软件学报》1995,6(Z1):52-58
本文基于多UIO序列提出了一种最优化协议一致性测试生成方法.可以证明本方法生成的测试序列的长度比其它基于UIO序列的测试方法生成的测试序列短.由于本方法采用了形式叠加技术,因此生成叠加转换序列所需要的计算时间大大减少了.  相似文献   

10.
基于单元故障模型的树型加法器的测试   总被引:4,自引:0,他引:4  
首先分析了树型加法器的原理,总结了其运算特性.其次在介绍单元故障模型的基础上分析了树型加法器的测试向量生成.分析结果表明,5n-1个测试向量可以实现树型加法器中所有单元故障的检测.这些测试向量具有很好的规则性,能够利用片上测试向量生成器实现,适合于应用内建自测试技术测试.基于此,作者提出了一种内建自测试的测试结构,测试时只需存储7个籽测试向量,其它测试向量可以在这7个籽测试向量的基础上通过循环移位实现.最后给出了实验分析结果.  相似文献   

11.
全速电流测试是一种新的电路测试方法,现以AT89C51微处理器为例,说明用全速电流测试进行微处理器测试的可能性.在实验中,让微处理器重复执行选定的指令序列,以普通的万用数字电流表测量微处理器消耗的平均电流,并给出了指令序列的产生方法.实验结果表明,用全速电流测试在指令级对AT89C51微处理器进行测试是可行的.通过测试所有的数据通路,不但可以检测数据通路的故障,而且可以检测由于控制错误而引起的数据传送错误.  相似文献   

12.
基于多故障模型的并发测试生成方法   总被引:1,自引:0,他引:1       下载免费PDF全文
精简测试向量集是解决电路测试问题的一种行之有效的方法。针对故障电路,采用多故障模型方法可以简化有多个单故障的电路,且保持电路功能完整。论文在结构分析的基础上,利用多故障模型寻找故障集中的并发故障,建立并发关系图,并运用分团的思想对故障集中的并发故障进一步划分,以获得故障集的并发测试集。与传统的方法相比,并发测试生成将获得更加精简的测试向量集。  相似文献   

13.
The partitioning of faults into equivalence classes so that only one representative fault per class must be explicitly considered in fault simulation and test generation, called fault collapsing, is addressed. Two types of equivalence, which are relevant to the work reported, are summarized. New theorems on fault equivalence and dominance, forming the basis of an algorithm that collapses all the structurally equivalent faults in a circuit, plus many of the functionally equivalent faults, are presented. Application of the algorithm to a set of benchmark circuits establishes that identification of functionally equivalent faults is feasible, and that, in some cases, they are a large fraction of the faults in a circuit. The collapsing algorithm applies not only to combinational designs but to synchronous sequential circuits as well  相似文献   

14.
IDDT: Fundamentals and Test Generation   总被引:5,自引:0,他引:5       下载免费PDF全文
It is the time to explore the fundamentals of IDDT testing when extensive work has been done for IDDT testing since it was proposed.This paper precisely defines the concept of average transient current(IDDT) of CMOS digital ICs,and experimentally analyzes the feasibility of IDDT test generation at gate level.Based on the SPICE simulation results,the paper suggests a formula to calculate IDDT by means of counting only logical up-transitions,which enables IDDT test generation at logic level.The Bayesian optimization algorithm is utilized for IDDT test generation.Experimental results show that about 25% stuck-open faults are with IDDT testability larger than 2.5,and likely to be IDDT testable.It is also found that most IDDT testable faults are located near the primary inputs of a circuit under test.IDDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation.Furthermore,some redundant stuck-at faults can be detected by using IDDT testing.  相似文献   

15.
Regression testing is an important activity in the software life cycle, but it can also be very expensive. To reduce the cost of regression testing, software testers may prioritize their test cases so that those which are more important, by some measure, are run earlier in the regression testing process. One potential goal of test case prioritization techniques is to increase a test suite's rate of fault detection (how quickly, in a run of its test cases, that test suite can detect faults). Previous work has shown that prioritization can improve a test suite's rate of fault detection, but the assessment of prioritization techniques has been limited primarily to hand-seeded faults, largely due to the belief that such faults are more realistic than automatically generated (mutation) faults. A recent empirical study, however, suggests that mutation faults can be representative of real faults and that the use of hand-seeded faults can be problematic for the validity of empirical results focusing on fault detection. We have therefore designed and performed two controlled experiments assessing the ability of prioritization techniques to improve the rate of fault detection of test case prioritization techniques, measured relative to mutation faults. Our results show that prioritization can be effective relative to the faults considered, and they expose ways in which that effectiveness can vary with characteristics of faults and test suites. More importantly, a comparison of our results with those collected using hand-seeded faults reveals several implications for researchers performing empirical studies of test case prioritization techniques in particular and testing techniques in general  相似文献   

16.
Phase change memory (PCM) is one of the most promising candidates for next generation nonvolatile memory. However, PCM suffers from a variety of faults due to its special device structure and operation mechanism. A snake addressing scheme is introduced into the test algorithms of PCM to reduce the test time and excite proximity disturb faults more effectively. The March test algorithm with the proposed snake addressing scheme is less complex than most traditional test algorithms. In addition to conventional faults, it is capable of covering disturb and parasitic faults. Moreover, when incorporated with the sneak path testing method, it is able to test the read fault, read recovery fault, incomplete program fault 0, and false write fault.  相似文献   

17.
Today's consumer electronics must be portable, reliable at various operating environments, and power efficient. Thus, semiconductor manufacturers constantly upgrade their production technologies and incorporate intelligent circuit design techniques. With widespread advances in system integration techniques, manufacturers can bundle multiple functionalities onto a single chip, reducing the end product's form factor. However, with higher levels of integration and reduced pin count, test issues are becoming more critical. During high-volume production, variations in process parameters cause devices to vary significantly from their performance metrics, and test engineers have only limited test resources to perform at-speed testing. Generating diagnosis information is also challenging during product ramp-up, as very little information is available from the output pins about the different modules' functionalities. DFT seems to be the only viable solution in such a scenario. DFT can address various issues related to at-speed testing and high-speed test response capture by performing signal conditioning to more easily capture information at lower speeds. The authors present a method that uses embedded DC sensors at test observation nodes to simplify data capture and enhance test quality while performing at-speed tests during production testing. Experiments show that monitoring sensor outputs provides a very good estimate of complex, system-level specifications.  相似文献   

18.
The authors present ScanBist, a low-overhead, scan-based built-in self-test method, along with its performance in several designs. A novel clock synchronization scheme allows at-speed testing of circuits. This design allows the testing of circuits operating at more than one frequency while retaining the combinational character of the circuit to be analyzed. We can therefore apply scan patterns that will exercise the circuit under test at the system speed, potentially providing a better coverage of delay faults when compared to other self-test methods. Modifications to an existing transition fault simulator account for cases where inputs originating from scan registers clocked at different frequencies drive a gate. We claim to detect transition faults only if the transition originates from the inputs driven by the highest frequency clock. ScanBist is useful at all levels of system packaging assuming that a standard TAP provides the control and boundary scan isolates the circuit from primary inputs and outputs during BIST mode  相似文献   

19.
Achieving at-speed structural test   总被引:1,自引:0,他引:1  
In addition to structural test, BIST offers an alternative low-cost approach to at-speed testing. How should BIST be implemented to address at-speed testing? What issues remain to be solved? How can we deal with multicycle paths and different frequency domains? The author describes BIST implementation techniques to answer these questions.  相似文献   

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