Application design for configurable computing

Configurable computing systems enhance traditional computing systems through the addition of programmable hardware. Configurable computing offers the opportunity to change the partition at run-time by re-programming the hardware. Recent research has shifted to CAD and application development tools. Almost all existing configurable computing systems are based on field-programmable gate arrays (FPGAs). These devices implement reasonably arbitrary digital circuits, and the flexibility allows us to think of configurable computing systems based on FPGAs as netlist computers. The configurable computing approach integrates FPGAs as an intimate and fundamental component of the computing system, rather than relegating them to their earlier role of supporting system prototyping and low-volume production. However, the author believes that automated approaches to the design of configurable computing systems are premature because they do not pay enough attention to performance     

The density advantage of configurable computing

More and more, field-programmable gate arrays (FPGAs) are accelerating computing applications. The absolute performance achieved by these configurable machines has been impressive-often one to two orders of magnitude greater than processor-based alternatives. Configurable computing is one of the fastest, most economical ways to solve problems such as RSA (Rivest-Shamir-Adelman) decryption, DNA sequence matching, signal processing, emulation, and cryptographic attacks. But questions remain as to why FPGAs have been so much more successful than their microprocessor and DSP counterparts. Do FPGA architectures have inherent advantages? Or are these examples just flukes of technology and market pricing? Will advantages increase, decrease, or remain the same as technology advances? Is there some generalization that accounts for the advantages in these cases? The author attempts to answer these questions and to see how configurable computing fits into the arsenal of structures used to build general, programmable computing platforms     

The Universal Configurable Block/Machine— An Approach for a Configurable SoC-Architecture

The universal configurable block/machine is a block-based approach for a configurable system-on-chip-(CSoC-) architecture. The programming model of the blocks is similar to microprocessor models, while the execution model supports configurable computing including reconfiguration. This is achieved by the microarchitecture of the blocks and an additional translation phase, resulting in three phases of overall program execution: fetching, translation and execution. These phases may act without strict coupling, simplifying the duplication of the executing part. The resulting hardware model is classified by four parameter: number of blocks, hyperblock sequencer, hyperblock scheduler and a set of block interconnections. The scheduler indicates that the model is capable of executing operating system work by scheduling hardware resources to threads or processes. This homogeneous CSoC may be used as compile-time defined inhomogeneous application-specific architecture. In this case the development process defines threads to run completely in one or more blocks solving partial problems and communicating to others. This enhances the flexibility and the optimization capabilities towards performance and/or real-time behavior.     

Seeking solutions in configurable computing

Configurable computing offers the potential of producing powerful new computing systems. Will current research overcome the dearth of commercial applicability to make such systems a reality? Unfortunately, no system to date has yet proven attractive or competitive enough to establish a commercial presence. We believe that ample opportunity exists for work in a broad range of areas. In particular, the configurable computing community should focus on refining the emerging architectures, producing more effective software/hardware APIs, better tools for application development that incorporate the models of hardware reconfiguration, and effective benchmarking strategies     

The wearARM modular, low-power computing core

The wearARM computing core for wearable applications uses highly miniaturized, mechanically flexible electronic packaging technology. Used with the MIThril platform, the system supports high-performance, low-power, user configurable wearable computing with wireless connectivity and local mass storage     

云计算技术浅析

云计算是一种按使用量付费的模式,该模式能提供可用的、便捷的、按需的网络访问,以进入可配置的计算资源共享池。这些资源能够被快速提供,而只需投入很少的管理工作,或与服务供应商进行很少的交互。云计算的到来,意味着用户将不再被地理位置所限制,而且不再被所使用的设备所限制。文章中对云计算技术进行了简单分析。     

Design and analysis of kinematically redundant parallel manipulators with configurable platforms

Redundancy can, in general, improve the ability and performance of parallel manipulators by implementing the redundant degrees of freedom to optimize a secondary objective function. Almost all published researches in the area of parallel manipulators redundancy were focused on the design and analysis of redundant parallel manipulators with rigid (nonconfigurable) platforms and on grasping hands to be attached to the platforms. Conventional grippers usually are not appropriate to grasp irregular or large objects. Very few studies focused on the idea of using a configurable platform as a grasping device. This paper highlights the idea of using configurable platforms in both planar and spatial redundant parallel manipulators, and generalizes their analysis. The configurable platform is actually a closed kinematic chain of mobility equal to the degree of redundancy of the manipulator. The additional redundant degrees of freedom are used in reconfiguring the shape of the platform itself. Several designs of kinematically redundant planar and spatial parallel manipulators with configurable platform are presented. Such designs can be used as a grasping device especially for irregular or large objects or even as a micro-positioning device after grasping the object. Screw algebra is used to develop a general framework that can be adapted to analyze the kinematics of any general-geometry planar or spatial kinematically redundant parallel manipulator with configurable platform.     

Parallel LU factorization of sparse matrices on FPGA‐based configurable computing engines

Configurable computing, where hardware resources are configured appropriately to match specific hardware designs, has recently demonstrated its ability to significantly improve performance for a wide range of computation‐intensive applications. With steady advances in silicon technology, as predicted by Moore's Law, Field‐Programmable Gate Array (FPGA) technologies have enabled the implementation of System‐on‐a‐Programmable‐Chip (SOPC or SOC) computing platforms, which, in turn, have given a significant boost to the field of configurable computing. It is possible to implement various specialized parallel machines in a single silicon chip. In this paper, we describe our design and implementation of a parallel machine on an SOPC development board, using multiple instances of a soft IP configurable processor; we use this machine for LU factorization. LU factorization is widely used in engineering and science to solve efficiently large systems of linear equations. Our implementation facilitates the efficient solution of linear equations at a cost much lower than that of supercomputers and networks of workstations. The intricacies of our FPGA‐based design are presented along with tradeoff choices made for the purpose of illustration. Performance results prove the viability of our approach. Copyright © 2004 John Wiley & Sons, Ltd.     

A Compiler Intermediate Representation for Reconfigurable Fabrics

Configurable computing relies on the expression of a computation as a circuit. Its main purpose is the hardware based acceleration of programs. Configurable computing has received renewed interest with the recent rapid increase in both size and speed of FPGAs. One of the major obstacles in the way of wider adoption of (re)configurable computing is the lack of high-level tools that support the efficient mapping of programs expressed in high-level languages (HLL) to reconfigurable fabrics. The major difficulty in such a mapping is the translation from a temporal execution model to a spatial execution model. An intermediate representation (IR) is the central structure around which tools such as compilers and synthesis tools are built. In this paper we propose an IR specifically designed for reconfigurable fabrics: CIRRF (Compiler Intermediate Representation for Reconfigurable Fabrics). We describe the design of CIRRF and its initial implementation as part of the ROCCC compiler for translating C code to VHDL. CIRRF is designed to support the creation of a datapath and the scheduling of operations on it. It provides support for buffers, look-up tables, predication and pipelining in the datapath. One of the important features of CIRRF, and ROCCC, is its support for the import of pre-designed IP cores into the original C source code allowing the user to leverage the huge wealth of existing IP cores while programming the configurable platform using a HLL. Using experiments and examples we show that CIRRF is a solid foundation to generate high-performance hardware.     

Video image processing with the Sonic architecture

Current industrial video-processing systems use a mixture of high-performance workstations and application-specific integrated circuits. However, video image processing in the professional broadcast environment requires more computational power and data throughput than most of today's general-purpose computers can provide. In addition, using ASICs for video image processing is both inflexible and expensive. Configurable computing offers an appropriate alternative for broadcast video image editing and manipulation by combining the flexibility, programmability, and economy of general-purpose processors with the performance of dedicated ASICs. Sonic is a configurable computing system that performs real-time video image processing. The authors describe how it implements algorithms for two-dimensional linear transforms, fractal image generation, filters, and other video effects. Sonic's flexible and scalable architecture contains configurable processing elements that accelerate software applications and support the use of plug-in software     

Configurable chips meld software and hardware

Processors that can be configured by end users promise to combine hardware's speed and efficiency with software's flexibility. Developments in configurable computing increasingly blur the line between hardware and software, a trend that represents a major shift in computing practice. To keep their offerings current and relevant, universities should modify their computer science curricula to better prepare students for this new era. Although hardware design is much more software-oriented now, aspiring computing students still need courses that cover hardware synthesis techniques, codesign methodologies, and module reuse strategies. Students should also experience working in teams. At our institute, we have developed such a new curriculum. By offering several hardware courses at both the elementary and advanced levels, we help students obtain a deeper and broader knowledge of configurable hardware design. Moreover, over the past few years we have invested in the design and construction of several FPGA-based boards for use as teaching platforms. These boards let students gain hands-on experience with technologies they'll use in real-world jobs. For example, using the Labomat board, a three-student team designed and tested a simplified floating-point unit in five three-hour sessions     

The FEDERICA infrastructure and experience

The European Commission co-funded project FEDERICA started in 2008 with the objective to support Future Internet research and experimentation. The project created a Europe-wide infrastructure based on virtualization in wired networks and computing elements, offering fully configurable and controllable virtual testbeds as a service to researchers. This article reviews the architecture, its deployment and current active status, usage experience, including virtual resource reproducibility and elaborates on challenges for Future Internet testbed support facilities.     

高性能异构多处理器平台及其应用

在视频编解码领域,随着视频图像分辨率的提高,对处理平台的计算能力、存储、传输带宽的需求急剧增加.为满足高分辨率视频编解码对处理平台的巨大性能需求,本文结合流处理器在媒体处理上的独特优势以及FPGA灵活的可配置性,构建了一个由流处理器和FPGA组成的可配置异构多处理器平台.为了对平台进行性能测试,将MOTION JPEG...     

Configurable parallel memory architecture for multimedia computers

This paper presents a novel parallel memory architecture for multimedia computers. Applying a configurable or programmable addressing circuitry capable of parallel memory accesses, the memory management of multimedia applications can be enhanced. Necessary computer architecture changes to virtual address representation, paging, virtual memory, address computation circuitry and data permutation are discussed. These changes allow the memory to be partitioned for different access functions. In addition, the same memory area can be accessed by multiple access patterns. Therefore, a general-purpose computing system that is capable of exploiting the repeating memory access patterns in its applications can be built. Performance of the configurable parallel memory architecture (CPMA) is analyzed in the case of a selection of algorithms from a video encoder. These motion estimation algorithms and zigzag scanning benefit from the multiple memory access functions, which is apparent from the comparisons to the traditional sequential memory accesses.     

天文图像差异算法的SoC实现

基于传输触发体系结构,设计一种可配置处理器T*Core,并将该处理器在现场可编程门阵列嵌入式平台上进行片上系统实现,完成AST3天文图像差异算法的数据密集型运算。应用结果表明,该设计可提高数据处理的实时性,减少硬件资源消耗,满足天文图像处理的需求。     

Achieving dynamic capabilities with cloud computing: an empirical investigation

Cloud computing enables convenient and on-demand access to a shared pool of configurable computing resources. While cloud computing‘s ability to improve operational efficiency has gained much attention in the literature, there has been limited research on how it can help organizations achieve dynamic capabilities. Drawing from dynamic capabilities theory, we conducted a field study using a multiple case study design to examine the following research question: How do organizations achieve dynamic capabilities by using Cloud Computing? We develop a framework that explains how organizations respond to market dynamism by developing sense-and-response strategies that enable them to achieve dynamic capabilities using business process redesign, business network redesign, and business scope redefinition. We discuss how these transformations, in turn, improve organizational outcomes such as service effectiveness and efficiency. Our study also identifies factors that support and hinder the development of dynamic capabilities. Our study contributes to the literature on dynamic capabilities by examining how IT capabilities like cloud computing may accelerate the ability of an organization to achieve dynamic capabilities. We also identify transformational changes of business processes and inter-organizational networks that are enabled by cloud computing. Further, we identify how the essential characteristics of cloud computing support sense and respond strategies.     

基于SaaS模式的信息系统架构优化研究与应用

SaaS模式作为云计算模式之一,有着多租户且可配置的特点。SaaS模式较好地解决了软件架构在扩展能力与资源共享等方面存在的问题。在研究中以SaaS信息系统架构在数据存储层与访问控制层方面所进行的分析为基础,确定了多稀疏表和键值对结合的模型,探讨了该模型所具有的优势。该研究对优化我国信息系统架构有一定的参考作用。