VFSim: Concurrent Fault Simulation at Register Transfer Level

VLSI testing is being pushed to the high-level based technology. In this paper a Verilog Register transfer level Model (VRM) for integrated circuits is proposed. The model provides a text format file, which is convenient and more practical for developing succeeding Register Transfer Level (RTL) test tools, such as fault simulation, test pattern generation and so forth. Based on the VRM, an RTL concurrent fault simulation approach is presented. After RTL fault models and super faults defined, the concurrent fault simulation algorithm is given. The corresponding RTL concurrent fault simulator, VFSim, was implemented. The initial experiments show that the RTL fault simulator is efficient for VLSI circuits.     

Generating test data for both path coverage and fault detection using genetic algorithms

The aim of software testing is to find faults in a program under test, so generating test data that can expose the faults of a program is very important. To date, current stud- ies on generating test data for path coverage do not perform well in detecting low probability faults on the covered path. The automatic generation of test data for both path coverage and fault detection using genetic algorithms is the focus of this study. To this end, the problem is first formulated as a bi-objective optimization problem with one constraint whose objectives are the number of faults detected in the traversed path and the risk level of these faults, and whose constraint is that the traversed path must be the target path. An evolution- ary algorithm is employed to solve the formulated model, and several types of fault detection methods are given. Finally, the proposed method is applied to several real-world programs, and compared with a random method and evolutionary opti- mization method in the following three aspects： the number of generations and the time consumption needed to generate desired test data, and the success rate of detecting faults. The experimental results confirm that the proposed method can effectively generate test data that not only traverse the target path but also detect faults lying in it.     

IDDT: Fundamentals and Test Generation

It is the time to explore the fundamentals of IDDT testing when extensive work has been done for IDDT testing since it was proposed.This paper precisely defines the concept of average transient current(IDDT) of CMOS digital ICs,and experimentally analyzes the feasibility of IDDT test generation at gate level.Based on the SPICE simulation results,the paper suggests a formula to calculate IDDT by means of counting only logical up-transitions,which enables IDDT test generation at logic level.The Bayesian optimization algorithm is utilized for IDDT test generation.Experimental results show that about 25% stuck-open faults are with IDDT testability larger than 2.5,and likely to be IDDT testable.It is also found that most IDDT testable faults are located near the primary inputs of a circuit under test.IDDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation.Furthermore,some redundant stuck-at faults can be detected by using IDDT testing.     

Adaptive output feedback control using fault compensation and fault estimation for linear system with actuator failure

The problem of linear systems subject to actuator faults（outage,loss of efectiveness and stuck）,parameter uncertainties and external disturbances is considered.An active fault compensation control law is designed which utilizes compensation in such a way that uncertainties,disturbances and the occurrence of actuator faults are account for.The main idea is designing a robust adaptive output feedback controller by automatically compensating the fault dynamics to render the close-loop stability.According to the information from the adaptive mechanism,the updating control law is derived such that all the parameters of the unknown input signal are bounded.Furthermore,a disturbance decoupled fault reconstruction scheme is presented to evaluate the severity of the fault and to indicate how fault accommodation should be implemented.The advantage of fault compensation is that the dynamics caused by faults can be accommodated online.The proposed design method is illustrated on a rocket fairing structural-acoustic model.     

Functional-Level Fault Simulation with Concurrent and Parallel Mechanisms Using Object-Oriented VLSI Model

The functional-level test has been proposed as an alternative to reduc the complexity of test when VLSI gets larger and more complicated.It has been successful for circuits such as memories,PLAs and microprocessors.However,the functional-level test for general functional models has sedldom been studied.This paper presents an object-oriented VLSI model and a functional-level fault simulation methodology for general functional model.Based on the proposed VLSI model,FFS(Functional-level Fault Simulator)with friendly visual interface has been implemented on Microsoft Windows platform by use of C .It is an integral part of MVS(Functional test Modeling and Verification System)--an extended subsystem of TeDS(Test Development System).The goal of FFS is to determine the fault coverage,generate fault dictionary and compact original test set at the function-level.In order to be efficient,FFS uses the concurrent and parallel mechanisms by taking advantage of the object-oriented VLSI model.The object-oriented VLSI model based fault simulation has been validated in the functional-level test by simulation results and the satisfying performance of FFS.     

Generating test data for both paths coverage and faults detection using genetic algorithms： multi-path case

Generating test data that can expose the faults of the program is an important issue in software testing. Al- though previous methods of covering path can generate test data to traverse target path, the test data generated by these methods are difficult in detecting some low-probabilistic faults that lie on the covered paths. We present a method of generating test data for covering multiple paths to detect faults in this study. First, we transform the problem of cover- ing multiple paths and detecting faults into a multi-objective optimization problem with constraint, and construct a mathe- matical model for it. Then, we give a strategy of solving the model based on a weighted genetic algorithm. Finally, we ap- ply our method to several real-world programs, and compare it with several methods. The experimental results confirm that the proposed method can more efficiently generate test data that not only traverse the target paths but also detect faults lying in them than other methods.     

Robustness assessment and adaptive FDI for car engine

A new on-line fault detection and isolation （FDI） scheme proposed for engines using an adaptive neural network classifier is evaluated for a wide range of operational modes to check the robustness of the scheme in this paper. The neural classifier is adaptive to cope with the significant parameter uncertainty, disturbances, and environment changes. The developed scheme is capable of diagnosing faults in on-line mode and the FDI for the closed-loop system with can be directly implemented in an on-board crankshaft speed feedback is investigated by diagnosis system （hardware）. The robustness of testing it for a wide range of operational modes including robustness against fixed and sinusoidal throttle angle inputs, change in load, change in an engine parameter, and all these changes occurring at the same time. The evaluations are performed using a mean value engine model （MVEM）, which is a widely used benchmark model for engine control system and FDI system design. The simulation results confirm the robustness of the proposed method for various uncertainties and disturbances.     

Robust fault detection for discrete-time Markovian jump systems with mode-dependent time-delays

This paper investigates a fault detection problem for a class of discrete-time Markovian jump systems with norm-bounded uncertainties and mode-dependent time-delays. Attention is focused on constructing the residual generator based on the filter of which its parameters matrices are dependent on the system mode, that is, the fault detection filter is a Markovian jump system as well. The design of fault detection filter is reduced to H-infinity filtering problem by using H-infinity control theory, which can guarantee the difference between the residual and the fault (or, more generally weighted fault) as small as possible in the context of enhancing the robustness of residual to modeling errors, control inputs and unknown inputs. Sufficient condition for the existence of the above filters is established by means of linear matrix inequalities, which can be readily solved by using standard numerical software. A numerical example is given to illustrate the feasibility of the proposed method.     

具有传输时延的网络控制系统故障估计与调节

In this paper,a method of fault estimation and fault tolerant control for networked control system (NCS) with transfer delay and process noise is presented.First,the networked control system is modeled as a multiple-input-multiple-output (MIMO) discrete-time system with transfer delays,process noise,and model uncertainties.Under this model and under some conditions, a fault estimation method is proposed to estimate the system faults.On the basis of the information on fault estimation and the sliding mode control theory,a fault tolerant controller is designed to recover the system performance. Finally, simulation results are used to verify the efficiency of the method.     

基于混合遗传算法的RTL激励生成

寄存器传榆级（RTL）描述是目前应用最广泛的电路设计描述形式．在时序电路的RTL激励生成中，基于模拟的方法避免了帧扩展法庞大的搜索空间，但采用该方法常存在向量过多．质量不高等问题．本文充分考虑影响算法效率的各种因素，在此基础上，提出一种基于混合遗传算法的激励生成方法．该方法结合多种覆盖评估准则与故障模型作为激励生成目标，同时采用动态参数设置，实现全局-局域混合搜索机制．实验结果显示该方法是有效的．     

寄存器传输级测试用例生成算法

基于控制流图／数据流图层次模型,以分支覆盖、位功能覆盖以及语句可观测覆盖为目标,给出一个高层次测试用例生成算法,并最终实现一种可行的RTL级测试生成算法．实验结果表明,在较少的测试生成时间下,该算法可生成相对短的测试序列,得到与其他方法相当或略差的测试效果．此外,该算法因采用了测试用例技术而具有良好的灵活性．     

综合模块化航空电子平台网络故障注入策略

综合模块化航空电子（IMA）平台网络通信结构复杂，在进行故障注入测试时，存在难以选取合适的测试路径及等效、无效故障注入较多的问题。根据IMA平台网络通信结构特点，提出一种新的故障注入策略。首先，根据IMA平台网络对实时性和确定性的要求，提出一种基于通信链路的测试路径优化算法，生成最优测试路径，实现对IMA平台网络测试任务的有序覆盖；然后，在确定测试路径之后，采用有色Petri网（CPN）建模方法搭建测试案例自动生成模型，排除等效与无效故障，精简测路径中每个测试任务所需的测试案例。仿真结果表明，所提方法在测试次数与测试时间等方面均少于传统的故障注入策略，能够克服传统策略中的无序性及盲目性的缺点，降低测试的时间成本。     

一种低功耗BIST测试方法

通过分析RTL的代码和RTL的故障仿真可得到一组屏蔽向量,将这些屏蔽向量和随机向量应用到门级进行故障测试可提高系统的故障覆盖率并降低测试功耗。本文主要论述了利用RTL的功能信息进行低功耗BIST测试的方法,并通过其在标准电路中的应用阐述实现过程。     

Correlation-based fault-tolerant controller design for MIMO systems under the Youla parameterisation

This paper develops a correlation-based method into the Youla parameterisation structure for a fault-tolerant controller design strategy. By tuning the Youla parameters with the proposed correlation-based algorithm, a number of conditional faults described by the dual Youla parameters are attenuated. The traditional fault-tolerant control (FTC) schemes under the Youla parameterisation often require the gradient information of the defined cost function for minimisation, which is either tedious or even unfeasible with unknown fault model. However, the proposed correlation-based FTC algorithm in this paper can compensate the faults via system data without the explicit fault model or the cost function gradient information. It is also proved that the algorithm convergence can be achieved without identifying the unknown fault model. For illustration, a simulation example with corresponding comparisons are presented to show the effectiveness of the proposed method in the end.     

完全RTL的故障数目预测及故障覆盖率计算

在超大规模集成电路设计过程中，门级故障仿真通常因仿真速度太慢而不能满足市场需求，因此近年来寄存器传输级(RTL)故障仿真成了一个研究热点．已有的RTL的故障模型和故障仿真方法在计算系统的故障覆盖率时，对故障数目或者加权系数的计算需要将RTL设计综合到门级．文中在信号位宽和运算符类型的基础上，提出了一种在RTL预测故障数的手段，并由此得到完全RTL的故障覆盖率计算方法．实验结果证明了该方法的有效性．     

Verilog到C翻译器的设计与实现

介绍了一种将Verilog硬件描述转化到等价C／C＋＋代码的自动翻译器的实现过程，并给出了简化Verilog行为模型的疗法、非阻塞赋值串行化的优化算法和一些访存优化原则。该方法没计的翻译器的生成代码可直接由C/C＋＋编译器汇编成可执行程序后进行仿真。采用龙芯RTL作为系统输入的测试表明，该方法的仿真速度可比一般仿真软件有成倍的增加，并能在系统评估和分析上发挥显著的成效。