Finding Communities by Decomposing and Embedding Heterogeneous Information Network

Community discovery is an important task in social network analysis.However,most existing methods for community discovery rely on the topological structure alone.These methods ignore the rich information available in the content data.In order to solve this issue,in this paper,we present a community discovery method based on heterogeneous information network decomposition and embedding.Unlike traditional methods,our method takes into account topology,node content and edge content,which can supply abundant evidence for community discovery.First,an embedding-based similarity evaluation method is proposed,which decomposes the heterogeneous information network into several subnetworks,and extracts their potential deep representation to evaluate the similarities between nodes.Second,a bottom-up community discovery algorithm is proposed.Via leader nodes selection,initial community generation,and community expansion,communities can be found more efficiently.Third,some incremental maintenance strategies for the changes of networks are proposed.We conduct experimental studies based on three real-world social networks.Experiments demonstrate the effectiveness and the efficiency of our proposed method.Compared with the traditional methods,our method improves normalized mutual information(NMI)and the modularity by an average of 12%and 37%respectively.     

Sensitivity analysis of distributed parameter elements in high-speed circuit networks

This paper presents an analysis method, based on MacCormack＇s technique, for the evaluation of the time domain sensitivity of distributed parameter elements in high-speed circuit networks. Sensitivities can be calculated from electrical and physical parameters of the distributed parameter elements. The proposed method is a direct numerical method of time-space discretization and does not require complicated mathematical deductive process. Therefore, it is very convenient to program this method. It can be applied to sensitivity analysis of general transmission lines in linear or nonlinear circuit networks. The proposed method is second-order-accurate. Numerical experiment is presented to demonstrate its accuracy and efficiency.     

A low-power DC offset calibration method independent of IF gain for zero-IF receiver

A novel low-power DC offset calibration(DCOC) method independent of intermediate frequency(IF) gain for zero-IF receiver applications has been reported. The conventional analog DCOC method consumes greater power and affects the performance of the receiver. The conventional mixed-signal method requires enhanced memory to store the calibration results at different receiver gains as the DC offset is relative to the radio frequency(RF) and IF gain. A novel algorithm is presented to make the DCOC process independent of IF gain, which significantly reduces the memory area. With the proposed circuit, the receiver calibrates only once so settle-time and power consumption of the IF circuit is lowered. A DCOC circuit with the proposed method is manufactured in 0.18 μm CMOS technology that drains nearly 0 mA equivalent current from a 1.8 V power supply.     

A low-power DC offset independent of IF gain calibration method for zero-IF receiver

A novel low-power DC offset calibration （DCOC） method independent of intermediate frequency （IF） gain for zero-IF receiver applications has been reported. The conventional analog DCOC method consumes greater power and affects the performance of the receiver. The conventional mixed-signal method requires enhanced memory to store the calibration results at different receiver gains as the DC offset is relative to the radio frequency （RF） and IF gain. A novel algorithm is presented to make the DCOC process independent of IF gain, which significantly reduces the memory area. With the proposed circuit, the receiver calibrates only once so settle-time and power consumption of the IF circuit is lowered. A DCOC circuit with the proposed method is manufactured in 0.18 p.m CMOS technology that drains nearly 0 mA equivalent current from a 1.8 V power supply.     

Fault-screen diagnosis approach for linear circuits with tolerance

A fault location approach for linear circuits with tolerance is proposed based on fault screen theory and optimization technology. By searching two sets of optimum excitation in a tolerance circuit, the voltage differences between faulty branches and normal ones can be exposed under every set of optimum excitation. A fault attaching function is established base on the voltage differences. Fault location is performed by means of the fault attaching function. Thus, fault screen strategy is applied to linear circuits with tolerance and fuzziness between fault and tolerance effort is greatly reduced. The experimental results show that the proposed approach can provide accurate and effective diagnosis.     

Maximum-likelihood detection based on branch and bound algorithm for MIMO systems

Maximum likelihood detection for MIMO systems can be formulated as an integer quadratic programming problem. In this paper, we introduce depth-first branch and bound algorithm with variable dichotomy into MIMO detection. More nodes may be pruned with this structure. At each stage of the branch and bound algorithm, active set algorithm is adopted to solve the dual subproblem. In order to reduce the complexity further, the Cholesky factorization update is presented to solve the linear system at each iteration of active set algorithm efficiently. By relaxing the pruning conditions, we also present the quasi branch and bound algorithm which implements a good tradeoff between performance and complexity. Numerical results show that the complexity of MIMO detection based on branch and bound algorithm is very low, especially in low SNR and large constellations.     

Flood Avoidance Mechanisms for Bridged Resilient Packet Rings

Resilient Packet Ring (RPR), or the Standard IEEE 802.17, is a new IP-based network technology proposed to replace SONET/SDH in metropolitan area networks. RPR is well-adapted to handle multimedia traffc and is effcient. However, when RPR networks are bridged, inter-ring packets, or packets with the destination on a remote RPR network other than on the source network, are flooded on the source and the destination networks, and also on the path of the intermediate networks between the source and the destination networks. This decreases the available bandwidth for other traffc in those networks and is ineffcient. As a result, we propose two solutions based on topology discovery, global topology discovery (GTD) and enhanced topology discovery (ETD), that prevent the flooding of inter-ring packets. GTD enables the bridges to determine the next-hop bridge for each destination. ETD enables the source node to determine a default ringlet, so that packets reach the next-hop bridge without flooding the source network. The proposed solutions were analyzed and the overhead bandwidth and stabilization time were shown to be bounded. Simulations performed showed that the proposed solutions successfully avoid flooding and achieve optimal effciency in the intermediate and destination networks, and in the source networks with one bridge.     

Emitter-couple logic circuit design based on the threshold-arithmetic algebraic system

Based on the threshold-arithmetic algebraic system which has been proposed for current-mode circuit design,we propose a systematic methodology for emitter-couple logic(ECL)circuit design.Compared to the traditional methodologies and the theory of differential current switches,the proposed methodology uses the HE map and the characteristics of the internal current signals of ECL circuits to determine the external voltage signals.The operations of the HE map are direct and simple,and the current signals are easy to add or subtract,which make this methodology more flexible,direct,and effective,and make it possible to design arbitrary binary and multi-valued logic functions.Two example circuits are designed and simulated by HSPICE using 0.18μm TSMC technology.Simulation results confirm the validity of the proposed methodology.     

Design of Quaternary ECL Q Gate

A new explanation of quaternary Q gate expression in Post algebra is given in this paper by using transmission function theory proposed in [1] and the quaternary ECL Q gate circuit is designed.The SPICE2 simulation to this circuit has confirmed that it has desired logical function and is totally compatible with various quaternary ECL circuits poposed before.     

The Methodology of Testability Prediction for Sequential Circuits

Increasingly,test generation algorithms are being developed with the continuous creations of incredibly sophisticated computing systems.Of all the developments of testable as well as reliable designs for computing systems,the test generation for sequential circuits is usually viewed as one of the hard nuts to be solved for its complexity and time-consuming issue.Although dozens of algorithms have been proposed to cope with this issue,it still remains much to be desired in solving such problems as to determin 1) which of the existing test generation algorithms could be the most efficient for some particular circuits(by efficiency,we mean the Fault Coverage the algorithm offers,CPU time when executing,the number of test patterns to be applied,ectc.)since different algorithms would be preferable for different circuits;2)which parameters(such as the number of gates,flip-flops and loops,etc., in the circuit)will have the most or least influences on test generation so that the designers of circuits can have a global understanding during the stage of designing for testability.Testability forecastin methodology for the sequential circuits using regression models is presented which a user usually needs for analyzing his own circuits and selecting the most suitable test generation algorithm from all possible algorithms available.Some examples and experiment results are also provided in order to show how helpful and practical the method is.     

基于几何多网格的RLC电源网络的瞬态模拟

提出了一种高效的、针对VLSI中Mesh拓扑结构的RLC电源线／地线网络的时域分析算法，该算法首次利用一种基于启发式原则的电路模型的简化方法来缩小电路网络的规模，扩展了原有的几何多网格方法来模拟求解以RLC元件建模的电源线网络．实验数据表明，对于一些规模较大的电路实例，在一个较小的误差损失下，该算法能大幅缩小电路的求解规模，求解速度比SPICE快两个数量级以上，比原有的几何多网格方法也有大幅的提高．如在Sun工作站上，当误差控制在1．5％时，模拟求解一个百万节点的电路网络仅仅需要半个小时．     

复杂模拟电路定量仿真中的元件建模技术研究

基于电路定量仿真的虚拟测试和故障诊断,对于复杂电路系统可靠性的提高具有重要意义;传统上,模拟电路的定量仿真分析大多采用SPICE模型,这也是目前该领域的主流分析模型;然而由于元件SPICE模型的复杂性,导致PSPICE等电路仿真器的优势难以在大型复杂电路系统的虚拟测试和故障诊断中得到充分发挥。为此,从降低元件模型复杂度,简化电路计算,提高仿真速度和避免收敛问题的角度出发,基于自主研制的DrGraph电路仿真平台,提出非线性二端元件SPICE模型的分段线性化改进技术。仿真实验验证了该技术在大规模复杂模拟电路仿真中具有很强的工程应用价值。     

基于部分随机行走的电源线/地线(P/G)网络快速求解方法

介绍一种基于随机行走方法与松弛迭代(SOR)算法相结合的快速电源网络求解方法，它先将P／G网分为若干块，然后用简化的随机行走方法求取电路块边界结点的电压，最后采用松弛迭代算法求出电路块内部结点的电压．同时还给出了一种电路块从对角顶点向中央求解的策略，并将此方法推广到采用RLC瞬态网络的求解．大量的实验数据表明，受限于P／G网供电PAD的数目较少这一现实，随机行走方法的效率比较低，在此情形下，该方法比随机行走方法快20倍．     

A scalable optoelectronic neural system using free-space opticalinterconnects

The design of a scalable, fully connected 3-D optoelectronic neural system that uses free-space optical interconnects with silicon-VLSI-based hybrid optoelectronic circuits is proposed. The system design uses a hardware-efficient combination of pulsewidth-modulating optoelectronic neurons and pulse-amplitude-modulating electronic synapses. Low-area, high-linear-dynamic-range analog synapse and neuron circuits are proposed. SPICE circuit simulations and an experimental demonstration of the free-space optical interconnection system are included.     

Analog-digital circuits for sound localization based on the biological auditory system

In this study, we propose an analog-digital circuit for sound localization based on the biological auditory system. The proposed circuit is constructed with a delay line and a comparator. The delay line was constructed with the simple analog circuits of the current mode. The NOR circuit was used as the comparator. The current mode delay line was evaluated by a simulation program with integrated circuit emphasis (SPICE). The test circuit was fabricated by discrete metal oxide semiconductor (MOS) transistors on the breadboard. The result with SPICE and the measured results of the test circuit showed that the time for transmitting a signal on the current mode delay line becomes shorter when the sound of the target is greater. When the sound of the target was small, the time taken to transmit the signal became longer. The proposed circuit for sound localization was evaluated by SPICE. The result with SPICE showed that the circuit can generate a signal to detect the position of the sound of the target. We can realize a new target-tracking system by applying this novel circuit based on the biological auditory system to a previously proposed tracking system based on the biological vision system.     

Threshold‐voltage‐compensation methods for AMOLED pixel and analog buffer circuits

Abstract— New pixel‐circuit designs for active‐matrix organic light‐emitting diodes (AMOLEDs) and a new analog buffer circuit for the integrated data‐driver circuit of active‐matrix liquid‐crystal displays (AMLCDs) and AMOLEDs, based on low‐temperature polycrystalline‐silicon thin‐film transistors (LTPS‐TFTs), were proposed and verified by SPICE simulation and measured results. Threshold‐voltage‐compensation pixel circuits consisting of LTPS‐TFTs, an additional control signal line, and a storage capacitor were used to enhance display‐image uniformity. A diode‐connected concept is used to calibrate the threshold‐voltage variation of the driving TFT in an AMOLED pixel circuit. An active load is added and a calibration operation is applied to study the influences on the analog buffer circuit. The proposed circuits are shown to be capable of minimizing the variation from the device characteristics through the simulation and measured results.     

基于Simulink的数模混合电路仿真平台设计与实现

针对数模混合电路仿真精度与性能之间的矛盾问题和仿真工业级复杂数模混合电路时仿真工具存在主流芯片和电路模块不足问题,提出了一种粘合模式的数模混合仿真平台模型架构,基于该架构设计并实现了一种基于Simulink软件,通过嵌入数字电路和模拟电路主流仿真引擎获得充足主流芯片和电路模块支持的数模混合电路仿真平台,设计了一种结合了拓扑排序算法的仿真控制方式,实现了对工业级复杂电路进行流程化、模块化的数模混合仿真;最后通过一个能够时序上可以逻辑拆分的典型数模混合电路仿真验证了仿真平台的有效性。     

基于电路拓扑结构分析的等价性验证方法

随着集成电路设计规模的日益增大,结合多种推理引擎已成为组合电路形式化等价性验证的重要手段.提出一种基于电路拓扑结构分析的组合等价性验证方法,将电路的拓扑结构与验证算法的复杂性关联起来.在验证过程开始之前,利用min-cut方法计算表征电路复杂性的"电路宽度",以确定最佳的推理引擎,避免了传统的引擎切换过程,提高了算法的效率.针对ISCAS85电路的实验结果表明了该方法的效率和可行性.     

基于斜率故障模型的模拟电路软故障字典法

提出了一种新的模拟电路故障字典法。与传统方法不同,该方法利用两个节点电压之间的关系函数作为故障特征。对于线性模拟电路,节点电压关系函数为一次函数,函数的斜率可以作为故障模型,同时可以诊断硬故障和参数(软)故障。由于模拟电路存在容差,最小直线距离法可以用于处理电路中的容差问题。