一种基于随机混合坐标表示的防功耗分析标量乘法实现方法

提出了一种新的防功耗分析(包括简单和差分功耗分析simpleanddifferentialpoweranalysis)的椭圆曲线标量乘法实现方法,该方法实现简单,并且适合于各种不同有限域上椭圆曲线标量乘法的实现.该方法以模乘和模加减操作为最小调度单位,将标量乘法转换成完全随机的模乘和模加减操作序列;基于随机混合坐标表示实现点的加法和倍加操作,并随机地从点的加法和倍加操作序列中选取后续的模乘和模加减操作;任务调度与模乘和模加减操作的执行是并行的.另外,本文定量分析了该实现方法对于功耗分析的防护能力以及运算性能.     

防范边信道攻击的逆伪操作实现算法

针对模幂运算的二元表示(BR)算法在防范边信道攻击方面存在的问题,以消除运算单元之间的功耗差异为目的,提出模幂运算的逆伪操作算法。通过对基本BR算法和逆伪操作算法的实测功耗轨迹对比和对逆伪操作算法防范边信道攻击分析,证明逆伪操作运算已达到消除运算单元之间功耗差异的预期目标。     

一种高效率的RSA模幂算法的研究

RSA硬件的执行效率主要取决于模幂运算的实现效率。该文旨在介绍一种引入中国剩余定理加速私钥操作,并采用Barret模缩减方法,避开除法运算,将模幂运算转换成三个乘法运算和一个加法运算的快速模幂算法及其硬件实现方法。在乘法运算的实现中,采用Booth乘法器,可以大大缩短电路的关键路径,显著地提高硬件的执行效率。     

RSA算法的一种高效软件实现方法

分析了RSA算法的软件实现难点为大数的幂模运算,提出了将大数的幂模运算转换为小数幂模运算乘积的高效方法,并实现了RSA算法,该方法在理论分析和试验方面都具有较好的效果。     

采用指令集扩展和随机调度的AES算法实现技术

在随机掩码技术基础上,定义了若干细粒度的随机掩码操作,将AES（Advanced Encryption Standard）算法中各种变换分解为细粒度随机掩码操作的序列,并使得所有的中间结果均被不同的随机量所掩码。为高效实现基于细粒度随机掩码操作分解的AES算法,定义了三种扩展指令,结合指令随机调度方法,给出了AES算法的完整实现流程,并指出这种实现技术可以抗一阶和高阶功耗攻击。实验结果表明,与其他典型防护技术相比,这种实现技术具有安全性、运算性能以及硬件复杂度等方面的综合优势。     

大整数模幂的固定基窗口组合算法

模幂乘运算是实现公钥密码体制的一个很重要的运算,其运算速度从整体上决定了公钥密码体制的实现效率。通过采用预处理技术,将椭圆曲线的定点标量乘的固定基窗口方法应用在模幂运算中,与SMM算法进行组合得到一种新的求模幂乘算法——固定基窗口方法。对算法的原理与效率进行了分析,实验结果表明,算法的运算速度得到了有效提高。     

基于n-bit协处理器的2n-bit RSA实现

借助模幂乘协处理器是提升RSA性能最有效的方法,但当RSA模幂运算长度超过协处理器能支持的最大运算长度时,协处理器将不再适用。本文针对这个问题,基于中国剩余定理和Fischer、Seifert算法,在n－bit模幂乘协处理器的基础上实现了模长为2n-bitRSA算法,并利用模幂乘协处理器实现了n－bit大数乘法和除法,进一步提高了RSA运算效率。     

基于支持向量机的RSA电磁旁路分析方法

针对在旁路分析过程中由于噪声的影响，不能直接观察出RSA的加密过程这一问题，提出结合支持向量机的旁路分析方法，从分类的角度对RSA二进制模幂运算中的平方、乘法操作进行识别，根据密钥与操作的相关性，推断出RSA二进制密钥序列。基于此，对移动设备PCM-9589F凌动主板进行了RSA电磁旁路分析研究，使用串口通信技术实现了对目标设备CPU的旁路电磁信号的采集，并采用基于边界的单类支持向量机的方法，以分类的正确率为70%为阈值，实现了对RSA二进制模幂运算中平方、乘法操作的识别，提取了OpenSSL加密库中1?024位RSA加密算法的二进制密钥序列。相比于传统的简单分析方法，克服了因旁路信号质量低而无法破解密钥的难题。     

智能卡中抗高阶功耗攻击AES算法实现技术

在提取AES算法中各种变换的公共操作的基础上,定义相应的基于随机掩码的原子操作,并以硬件方式实现。将AES算法中各种变换转换为随机掩码原子操作的序列,密码算法运算过程中使用不同的随机量对所有中间结果进行掩码。在此基础上,以软硬件结合的方式实现AES算法,掩码的原子操作以硬件方式实现,而运算流程控制以软件方式实现;并且结合运算流程随机化技术进一步提高实现的安全性。安全分析表明,这种实现技术可以抗一阶功耗攻击和高阶功耗攻击。实验结果表明,所提出的AES算法实现方法的硬件实现开销较小,并且具有高安全性,适合于智能卡实现。     

多差异嵌入式设备的节能任务调度模型仿真

在一些复杂嵌入式设备联合工作的环境下,设备之间的工作关系差异较大,存在较为复杂的能量消耗制约关系,不再呈现简单的线性调度关系。为了制约这种大差异的环境,嵌入式设备任务与任务之间的最优化节能调度过程存在大量的顺序约束关系,导致传统的多差异嵌入式设备节能任务调度模型,只能采用近似算法模糊化表述复杂约束关系,不能适应调度任务的非线性大规模变化,无法实现多差异嵌入式设备的节能任务调度。提出一种基于遗传算法的多差异嵌入式设备的任务调度模型,依据功耗最低化原则,通过遗传算法将任务集中的任务以特定频率分配到各个多差异嵌入式设备中进行处理,使得总能耗达到最小,建立设备功耗模型,实现设备的节能任务调度。仿真结果表明,所提方法具有较高的节能性及有效性。     

An efficient common-multiplicand-multiplication method to the Montgomery algorithm for speeding up exponentiation

The modular exponentiation is a common operation for scrambling secret data and is used by several public-key cryptosystems, such as the RSA scheme and DSS digital signature scheme. However, the calculations involved in modular exponentiation are time-consuming especially when performed in software. In this paper, we propose an efficient CMM-MSD Montgomery algorithm by utilizing the Montgomery modular reduction method, common-multiplicand-multiplication (CMM) method, and minimal-signed-digit (MSD) recoding technique for fast modular exponentiation. By using the technique of recording the common signed-digit representations in the grouped substrings of exponent, our algorithm can improve the efficiency of both the original CMM exponentiation algorithm and the Montgomery multiplication algorithm. The fast modular exponentiation algorithm developed in this paper can be easily implemented in general signed-digit computing machine, and is therefore well suited for parallel implementation to fast evaluating modular exponentiation. Moreover, by using the proposed CMM-MSD Montgomery algorithm, on average the total number of single-precision multiplications can be reduced by about 38.9% and 26.68% as compared with Dusse-Kaliski’s Montgomery algorithm and Ha-Moon’s Montgomery algorithm, respectively.     

High-Performance Hardware of the Sliding-Window Method for Parallel Computation of Modular Exponentiations

Modular exponentiation is a basic operation in various applications, such as cryptography. Generally, the performance of this operation has a tremendous impact on the efficiency of the whole application. Therefore, many researchers have devoted special interest to providing smart methods and efficient implementations for modular exponentiation. One of these methods is the sliding-window method, which pre- processes the exponent into zero and non-zero partitions. Zero partitions allow for a reduction of the number of modular multiplications required in the exponentiation process. In this paper, we devise a novel hardware for computing modular exponentiation using the sliding-window method. The partitioning strategy used allows variable-length non-zero partitions, which increases the average number of zero partitions and so decreases that of non-zero partitions. It performs the partitioning process in parallel with the pre-computation step of the exponent so no overhead is introduced. The implementation is efficient when compared against related existing hardware implementations.     

模重复平方算法的rho改进算法

利用循环二进制方法给出了适合大指数模乘运算的模重复平方算法的rho改进算法,以提高模幂乘法的计算速度。新算法的实质是一种指数约减算法,可以有效减少模重复平方算法中的模乘运算。通过实例计算表明,新算法可以极大地提高运算速度。     

大数模幂乘动态匹配快速算法及其应用

针对 RSA、Elgamal、DSA等算法在进行数据加密或数字签名时都要进行复杂的大数模幂乘运算 ,本文分析了目前常用的几种大数模幂乘算法 ,并在此基础上提出了一种动态匹配快速算法 .实验表明 ,将该算法用于实现 RSA算法 ,其实现速度较其他算法有明显提高 .     

快速实现数字签名的宏观加模算法

提出一种宏观累加模的快速模幂乘的算法,将乘法运算和求模运算转换成简单的移位运算和加法运算,从而避免了求模运算和减少大数相乘次数。实验表明,本算法可以用接近n/2次n-bit的加法运算即可实现A×BmodN运算,在宏观上看,计算C=me要比Montgomery等算法快2倍。     

Parallel modular exponentiation using load balancing without precomputation

The modular exponentiation operation of the current algorithms for asymmetric cryptography is the most expensive part in terms of computational cost. The RSA algorithm, for example, uses the modular exponentiation algorithm in encryption and decryption procedure. Thus, the overall performance of those asymmetric cryptosystems depends heavily on the performance of the specific algorithm used for modular exponentiation. This work proposes new parallel algorithms to perform this arithmetical operation and determines the optimal number of processors that yields the greatest speedup. The optimal number is obtained by balancing the processing load evenly among the processors. Practical implementations are also performed to evaluate the theoretical proposals.     

Fast exponentiation by folding the signed-digit exponent in half

For modern cryptographic systems, the public key cryptosystem such as RSA requires modular exponentiation (M ^E mod?N). The M, E and N are either as large as the 1024-bit integers or even larger, it is not a very good idea to directly compute M ^E mod?N. Recently, there are many techniques have been invented to solve the time-consuming computations of such time-consuming modular exponentiation. Among these useful algorithms, the “binary (square-and-multiply) algorithm” reduces the amount of modulo multiplications. As the “signed-digit representation algorithm” has the property of the nonzero digit occurrence probability equals to 1/3, taking this advantage, this method can more effectively decrease the amount of modular multiplications. Moreover, by using the technique of recording the common parts in the folded substrings, the “folding-exponent algorithm” can improve the efficiency of the binary algorithm, thus can further decrease the computational complexity of modular exponentiation. In this paper, a new modular exponentiation algorithm is proposed which based on the binary algorithm, signed-digit representation, and the folding-exponent technique. By using the parallel processing technique, in our proposed method, the modular multiplications and modular squaring can be executed in parallel, and thus lower down the computational complexity to k?+?3 multiplications. As modular squaring operation over GF(2 ⁿ ) is carried out by a simple cyclic right shift operation, the computational complexity of our proposed method can be further reduced to 29k/36?+?3 multiplications.     

RSA算法的一种DSP快速实现*

根据DSP特性采用了RSA模幂快速算法,在节省了主机资源的同时加速了RSA算法;另一方面,方案采用密钥拆分机制,使得完整私钥对于外界是无法访问的,同时提高了RSA算法在实际应用中的安全性。