Computer simulation of the transmission of modulated signals through linear analog circuits using fast Fourier transforms

An algorithm is proposed for computing transformations of modulated signals in linear circuits by the spectrum method and by applying fast Fourier transforms. The algorithm computes transformations of oscillations with complex modulation and large angle modulation indexes in analog circuits. The accuracy of the proposed method is discussed. A program is described for analyzing modulated oscillations in linear selective circuits that complements the known electronic circuit simulation programs. Translated from Izmeritel'naya Tekhnika, No. 8, pp. 38–40, August, 1998.     

On the implementation of an analog ATPG: the nonlinear case

In order to reduce the complexity of the fault diagnosis equations and still retain computational simplicity, a self-testing algorithm has been proposed and implemented on a VMS VAX 11/780 for linear circuits. A prototype implementation of such an algorithm for nonlinear circuits and systems is presented. The proposed analog automatic test program generator (AATPG) for nonlinear circuits and systems is divided into offline and online processes. Unlike the simulation of the pseudocircuits in the linear case, which can be achieved by a matrix/vector multiplication, the circuit simulator SPICE is used to simulate the nonlinear pseudocircuits. The automatic SPICE code generator required for this simulation is presented. The proposed AATPG for nonlinear circuits has been implemented on a VMS VAX 11/780. The actual test can be run in either a fully automatic mode or interactively     

Electromodeling of solutions of fourier differential equations

An examination is made of some aspects of the modeling of heat conduction or diffusion process described by Fourier equations on analog computers. A scheme is given for reproducing a sum of exponential functions with the aid of a single amplifier and a group of switching circuits.     

数字电路可测性设计的一种故障定位方法

在逻辑函数ReedMuller模式的电路可测性设计方面，文章采用AND门阵列和XOR门树结构来设计电路，提出了一种设计方案，可实现任意逻辑函数的功能，而且所得电路具有通用测试集和完全可故障定位的特点。给出了进行故障定位的方法，并可把它应用于其他相关电路的可测性设计。     

Programmable DNA Nanoindicator‐Based Platform for Large‐Scale Square Root Logic Biocomputing

The prospect of programming molecular computing systems to realize complex autonomous tasks has advanced the design of synthetic biochemical logic circuits. One way to implement digital and analog integrated circuits is to use noncovalent hybridization and strand displacement reactions in cell‐free and enzyme‐free nucleic acid systems. To date, DNA‐based circuits involving tens of logic gates capable of implementing basic and complex logic functions have been demonstrated experimentally. However, most of these circuits are still incapable of realizing complex mathematical operations, such as square root logic operations, which can only be carried out with 4 bit binary numbers. A high‐capacity DNA biocomputing system is demonstrated through the development of a 10 bit square root logic circuit. It can calculate the square root of a 10 bit binary number (within the decimal integer 900) by designing DNA sequences and programming DNA strand displacement reactions. The input signals are optimized through the output feedback to improve performance in more complex logical operations. This study provides a more universal approach for applications in biotechnology and bioengineering.     

Oscillation-test methodology for low-cost testing of active analogfilters

The oscillation-test strategy is a low cost and robust test method for mixed-signal integrated circuits. Being a vectorless test method, it allows one to eliminate the analog test vector generator. Furthermore, as the oscillation frequency is considered to be digital, it can be precisely analyzed using pure digital circuitry and can be easily interfaced to test techniques dedicated to the digital part of the circuit under test (CUT). This paper describes the design for testability (DFT) of active analog filters based on oscillation-test methodology. Active filters are transformed to oscillators using very simple techniques. The tolerance band of the oscillation frequency is determined by a Monte Carlo analysis taking into account the nominal tolerance of all circuit under test components. Discrete practical realizations and extensive simulations based on CMOS 1.2 μm technology parameters affirm that the test technique presented for active analog filters ensures high fault coverage and requires a negligible area overhead. Finally, the DFT techniques investigated are very suitable for automatic testable filter synthesis and can be easily integrated in the tools dedicated to automatic filter design     

一种新的模拟电路故障模糊集确定算法

提出了一种在模拟电路故障诊断中故障类模糊集的确定算法．该算法基于测前仿真法,不但同时适用于线性电路和非线性电路,而且可以确定元件模糊组以外的故障类模糊集．算法利用电路仿真故障特征数据计算故障的类间差异矩阵,从而完成故障类模糊集的确定．计算示例验证了该算法的有效性．     

Automated selection of test frequencies for fault diagnosis in analog electronic circuits

This paper suggests three novel methods for selecting the frequencies of sinusoidal test signals to be used in fault diagnosis of analog electronic circuits. The first and second methods are based on a sensitivity analysis and show to be particularly effective in linear circuits where a priori information and designer experience can be exploited. Conversely, the third method selects the input frequencies to be used for diagnostic purposes without requiring any hypothesis about the circuit or testing design background. As such, the method is particularly appealing in complex -possibly nonlinear - circuits where the designer experience is of little value and an effective "blind" approach saves both designer and testing time. The suggested frequency selection methods are then contrasted to each other against performance and computational complexity.     

Testing Analog and Mixed-Signal Circuits With Built-In Hardware—A New Approach

This paper aims to develop an approach to test analog and mixed-signal embedded-core-based system-on-chips (SOCs) with built-in hardware. In particular, oscillation-based built-in self-test (OBIST) methodology for testing analog components in mixed-signal circuits is implemented in this paper. The proposed OBIST structure is utilized for on-chip generation of oscillatory responses corresponding to the analog-circuit components. A major advantage of the OBIST method is that it does not require stimulus generators or complex response analyzers, which makes it suitable for testing analog circuits in mixed-signal SOC environments. Extensive simulation results on sample analog and mixed-signal benchmark circuits and other circuits described by netlist in HSPICE format are provided to demonstrate the feasibility, usefulness, and relevance of the proposed implementations     

Test limitations of parametric faults in analog circuits

This paper investigates the detectability of parameter faults in linear, time-invariant, analog circuits and sheds new light on a number of very important test attributes. We show that there are inherent limitations with regard to analog faults detectability. It is shown that many parameter faults are undetectable irrespective of which test methodology is being used to catch them. It is also shown that, in many cases, the detectable minimum-size parameter fault is considerably larger than the normal parameter drift. Sometimes the minimum-size detectable fault is two to five times the parameter drift. We show that one of the fault-masking conditions in analog circuits, commonly believed to be true, is, in fact, untrue. We illustrate this with a simple counter example. We also show that, in analog circuits, it is possible for a fault-free parameter to mask an otherwise detectable parametric fault. We define the small-size parameter fault coverage, and describe ways to calculate or estimate it. This figure of merit is especially suitable in characterizing the test efficiency in the presence of small-size parameter faults. We further show that circuit specification requirements may be translated into parameter tolerance requirements. By doing so, a test for parametric faults can, indirectly, address circuit specification compliance. The test limitations of parametric faults in analog circuits are illustrated using numerous examples.     

Synaptic Resistors for Concurrent Inference and Learning with High Energy Efficiency

The fastest supercomputer, Summit, has a speed comparable to the human brain, but is much less energy‐efficient (≈10¹⁰ FLOPS W^?1, floating point operations per second per watt) than the brain (≈10¹⁵ FLOPS W^?1). The brain processes and learns from “big data” concurrently via trillions of synapses in parallel analog mode. By contrast, computers execute algorithms on physically separated logic and memory transistors in serial digital mode, which fundamentally restrains computers from handling “big data” efficiently. The existing electronic devices can perform inference with high speeds and energy efficiencies, but they still lack the synaptic functions to facilitate concurrent convolutional inference and correlative learning efficiently like the brain. In this work, synaptic resistors are reported to emulate the analog convolutional signal processing, correlative learning, and nonvolatile memory functions of synapses. By circumventing the fundamental limitations of computers, a synaptic resistor circuit performs speech inference and learning concurrently in parallel analog mode with an energy efficiency of ≈1.6 × 10¹⁷ FLOPS W^?1, which is about seven orders of magnitudes higher than that of the Summit supercomputer. Scaled‐up synstor circuits could circumvent the fundamental limitations in computers, and facilitate real‐time inference and learning from “big data” with high efficiency and speed in intelligent systems.     

Block-indexed solution of very large linear equation systems with symmetric dbbf coefficient matrix

The finite element solution of various partial differential equations leads to large linear equation systems, which may have a DBBF (double bounded band form) coefficient matrix, if periodicity conditions are taken into account. An efficient Fortran program solving such equation systems, developed for Control Data computers from the Cyber 70/170 series, utilizes the original block-indexed approach to reduce input-output time in communication with disc memory. Program performance is presented in some detail and quantitative comparison with other possible algorithms is carried out. An appendix lists the complete program.     

Signal processing: Opportunities for superconductive circuits

Prime motivators in the evolution of increasingly sophisticated communication and detection systems are the needs for handling ever wider signal bandwidths and higher data processing speeds. These same needs drive the development of electronic device technology. Until recently the superconductive community has been tightly focused on digital devices for high speed computers. The purpose of this paper is to describe opportunities and challenges which exist for both analog and digital devices in a less familiar area, that of wideband signal processing. The function and purpose of analog signal-processing components, including matched filters, correlators and Fourier transformers, will be described and examples of superconductive implementations given. A canonic signal-processing system is then configured using these components in combination with analog/digital converters and digital output circuits to highlight the important issues of dynamic range, accuracy and equivalent computation rate. Superconductive circuits hold promise for processing signals of 10-GHz bandwidth. Signal processing systems, however, can be properly designed and implemented only through a synergistic combination of the talents of device physicists, circuit designers, algorithm architects and system engineers. An immediate challenge to the applied superconductivity community is to begin sharing ideas with these other researchers.     

POD surrogates for real-time multi-parametric sheet metal forming problems

Our approach aims at coupling the ever increasing off-line computing power of mainframe computers with the interactive on-line possibilities of ubiquitous low computing power devices at the early design stages in order to provide insight into the design problems and to search for candidate optimal design points. In the off-line phase, the method under investigation relies on combining an optimized space-filling sampling plan on the design parameter space with extensive finite elements (FE) simulations yielding a learning set of displacement fields. The objective of this paper is the on-line phase. We provide a rigorous mathematical presentation of a family of non-intrusive, bi-level surrogates. We focus on displacement field approximation by Proper Orthogonal Decomposition (POD) combined with kriging interpolation of coefficients. The method is illustrated with two simple, easily reproduced numerical examples of quality assessment of deep-drawing process of a cylindrical cup by on-the-fly plotting forming limit diagrams (FLDs) and related quantities enabling thus to spot improved design points.     

Analog Modeling Improves Test Programs

The complexity of integrated circuits has increased to the point that the integrated circuit's (IC) internal circuit components affect the ability of in-circuit testers to accurately measure analog components connected externally to the IC. For analog circuit analyzers, the ability to describe the IC's internal electrical equivalent using standard components, R, L, C, etc., improves the automatic analog test program generator's ability to add guards to offset the internal shunts. This article presents a technique for selecting and describing basic component types and component magnitudes within the IC's internal structure.     

Developing linear error models for analog devices

Techniques are presented for developing linear error models for analog and mixed-signal devices. A simulation program developed to understand the modeling process is described, and results of simulations are presented. Methods for optimizing the size of empirical error models based on simulated error analyses are included. Once established, the models can be used in a comprehensive approach for optimizing the testing of the subject devices. Models are developed using data from a group of 13-bit A/D converters and compared with the simulation results     

On the Implementation of an Analog ATPG: The Linear Case

A self-testing algorithm in which post-test simulation with failure bounds is employed, has been proposed. Based on this self-testing algorithm, an analog Automatic Test Program Generation (ATPG) for linear circuits or systems is being developed. The AATPG code is subdivided into off-line and on-line components while the actual test can be run in either a fully automatic mode or interactively.     

A Design of a Period-to-Frequency Analog Converter

A method for designing a period-to-analog converter is described. The device accepts input signals of varying frequency and converts the period of the waveform to a time inverse voltage Vi(t). This voltage is sampled at the end of the period, and this information is held over the following interval. The analog derived from the input signal is a voltage proportional to the repetition rate. The approach to generating the time inverse voltage is based on Willer's general method of approximating decaying functions with a sum of exponential functions. The described method has been utilized to develop a device for monitoring physiological signals. Results demonstrating the performance of the instrument are presented. The method is directly applicable to function generation in general and could be of importance for analog computers.