A generalised uncertain decision tree for defect classification of multiple wafer maps

Classification of defect chip patterns is one of the most important tasks in semiconductor manufacturing process. During the final stage of the process just before release, engineers must manually classify and summarise information of defect chips from a number of wafers that can aid in diagnosing the root causes of failures. Traditionally, several learning algorithms have been developed to classify defect patterns on wafer maps. However, most of them focused on a single wafer bin map based on certain features. The objective of this study is to propose a novel approach to classify defect patterns on multiple wafer maps based on uncertain features. To classify distinct defect patterns described by uncertain features on multiple wafer maps, we propose a generalised uncertain decision tree model considering correlations between uncertain features. In addition, we propose an approach to extract uncertain features of multiple wafer maps from the critical fail bit test (FBT) map, defect shape, and location based on a spatial autocorrelation method. Experiments were conducted using real-life DRAM wafers provided by the semiconductor industry. Results show that the proposed approach is much better than any existing methods reported in the literature.     

Boosted Stacking Ensemble Machine Learning Method for Wafer Map Pattern Classification

Recently, machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductor manufacturing. The existing approaches used in the wafer map pattern classification include directly learning the image through a convolution neural network and applying the ensemble method after extracting image features. This study aims to classify wafer map defects more effectively and derive robust algorithms even for datasets with insufficient defect patterns. First, the number of defects during the actual process may be limited. Therefore, insufficient data are generated using convolutional auto-encoder (CAE), and the expanded data are verified using the evaluation technique of structural similarity index measure (SSIM). After extracting handcrafted features, a boosted stacking ensemble model that integrates the four base-level classifiers with the extreme gradient boosting classifier as a meta-level classifier is designed and built for training the model based on the expanded data for final prediction. Since the proposed algorithm shows better performance than those of existing ensemble classifiers even for insufficient defect patterns, the results of this study will contribute to improving the product quality and yield of the actual semiconductor manufacturing process.     

Yield prediction via spatial modeling of clustered defect counts across a wafer map

In this paper we propose spatial modeling approaches for clustered defects observed using an Integrated Circuit (IC) wafer map. We use the spatial location of each IC chip on the wafer as a covariate for the corresponding defect count listed in the wafer map. Our models are based on a Poisson regression, a negative binomial regression, and Zero-Inflated Poisson (ZIP) regression. Analysis results indicate that yield prediction can be greatly improved by capturing the spatial distribution of defects across the wafer map. In particular, the ZIP model with spatial covariates shows considerable promise as a yield model since it additionally models zero-defective chips. The modeling procedures are tested using a practical example.     

Multi-step ART1 algorithm for recognition of defect patterns on semiconductor wafers

The integrated circuits (ICs) on wafers are highly vulnerable to defects generated during the semiconductor manufacturing process. The spatial patterns of locally clustered defects are likely to contain information related to the defect generating mechanism. For the purpose of yield management, we propose a multi-step adaptive resonance theory (ART1) algorithm in order to accurately recognise the defect patterns scattered over a wafer. The proposed algorithm consists of a new similarity measure, based on the p-norm ratio and run-length encoding technique and pre-processing procedure: the variable resolution array and zooming strategy. The performance of the algorithm is evaluated based on the statistical models for four types of simulated defect patterns, each of which typically occurs during fabrication of ICs: random patterns by a spatial homogeneous Poisson process, ellipsoid patterns by a multivariate normal, curvilinear patterns by a principal curve, and ring patterns by a spherical shell. Computational testing results show that the proposed algorithm provides high accuracy and robustness in detecting IC defects, regardless of the types of defect patterns residing on the wafer.     

A discrete spatial model for wafer yield prediction

Yield analysis is one of the key concerns in the fabrication of semiconductor wafers. An effective yield analysis model will contribute to production planning and control, cost reductions and the enhanced competitiveness of enterprises. In this article, we propose a novel discrete spatial model based on defect data on wafer maps for analyzing and predicting wafer yields at different chip locations. More specifically, based on a Bayesian framework, we propose a hierarchical generalized linear mixed model, which incorporates both global trends and spatially correlated effects to characterize wafer yields with clustered defects. Both real and simulated data are used to validate the performance of the proposed model. The experimental results show that the newly proposed model offers an improved fit to spatially correlated wafer map data.     

Automatic identification of spatial defect patterns for semiconductor manufacturing

This research proposes an on-line diagnosis system based on denoising and clustering techniques to identify spatial defect patterns for semiconductor manufacturing. Today, even with highly automated and precisely monitored facilities used in a near dust-free clean room and operated with well-trained process engineers, the occurrence of spatial signatures on the wafer still cannot be avoided. Typical defect patterns shown on the wafer, including edge ring, linear scratch, zone type and mixed type, usually contain important information for quality engineers to remove their root causes of failures. In this paper, a spatial filter is simultaneously used to judge whether the input data contains any systematic cluster and to extract it from the noisy input. Then, an integrated clustering scheme combining fuzzy C means (FCM) with hierarchical linkage is adopted to separate various types of defect patterns. Furthermore, a decision tree based on two cluster features (convexity and eigenvalue ratio) is applied to a separated pattern to provide decision support for quality engineers. Experimental results show that both real dataset and synthetic dataset have been successfully extracted and classified. More importantly, the proposed method has potential to be further applied to other industries, such as liquid crystal display (LCD) and plasma display panel (PDP).     

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.     

Wafer bin map recognition using a neural network approach

Although the fabrication of modern integrated circuits uses highly automatic and precisely controlled operations, equipment malfunctions or process drifts are still inevitable owing to the high complexity involved in the hundreds of processing steps. To detect the existence of these problems at the earliest stage, some important analytical tools must be applied. Among them is wafer bin map analysis. When the bin map exhibits specific patterns, it is usually a clue that equipment problems or process variations have occurred. The aim was to develop an intelligent system that could automatically recognize wafer bin map patterns and aid in the diagnosis of failure causes. A neural network architecture named Adaptive Resonance Theory Network 1 was adopted for the purpose. Actual data collected from a semiconductor manufacturing company in Taiwan were used for system verification. Experimental results show that with an adequate parameter, the neural network can successfully recognize and distinguish random and systematic wafer bin map patterns.     

CAD navigation and diagnostics by linking ATE and EDA

This paper describes a specific methodology and software that links automated test equipment (ATE) and electronic design automation (EDA) tools to identify and diagnose failures at the layout level. The ATE software, named wafer fail layout map (WFLMAP), works in concert with the EDA integrated circuits (IC) design database and provides computer-aided design (CAD) navigation and correlation between the tester failure data and IC design data. With this approach, layout-level defect diagnosis is achieved at the individual chip level, as well as at the wafer level. This method can also be used for improved design for manufacturing (DFM).     

A model-based clustering approach to the recognition of the spatial defect patterns produced during semiconductor fabrication

Defects on semiconductor wafers tend to cluster and the spatial defect patterns of these defect clusters contain valuable information about potential problems in the manufacturing processes. This study proposes a model-based clustering algorithm for automatic spatial defect recognition on semiconductor wafers. A mixture model is proposed to model the distributions of defects on wafer surfaces. The proposed algorithm can find the number of defect clusters and identify the pattern of each cluster automatically. It is capable of detecting defect clusters with linear patterns, curvilinear patterns and ellipsoidal patterns. Promising results have been obtained from simulation studies.     

Minimizing the total machine workload for the wafer probing scheduling problem

The Wafer Probing Scheduling Problem (WPSP) is a practical generalization of the parallel-machine scheduling problem, which has many real-world applications, particularly, in the Integrated Circuit (IC) manufacturing industry. In the wafer probing factories, the jobs are clustered by their product types, which must be processed on groups of identical parallel machines and be completed before the due dates. The job processing time depends on the product type, and the machine setup time is sequentially dependent on the orders of jobs processed. Since the wafer probing scheduling problem involves constraints on job clusters, job-cluster dependent processing time, due dates, machine capacity, and sequentially dependent setup time, it is more difficult to solve than the classical parallel-machine scheduling problem. In this paper, we consider the WPSP and formulate the WPSP as an integer programming problem to minimize the total machine workload. We demonstrate the applicability of the integer programming model by solving a real-world example taken from a wafer probing shop floor in an IC manufacturing factory.     

基于DCAE-CNN的自动倾斜器滚动轴承故障诊断

针对直升机自动倾斜器滚动轴承工况复杂、噪声干扰大,造成故障诊断效果不佳的问题,提出一种基于深度卷积自编码器(Deep Convolutional AutoEncoder,DCAE)和卷积神经网络(Convolutional Neural Network,CNN)的轴承故障诊断方法。该方法首先采用小波变换方法构造不同状态下振动信号的时频图,然后使用DCAE对时频图进行图像去噪,最后利用CNN对去噪后的时频图进行故障分类。利用课题组和美国凯斯西储大学的滚动轴承故障数据开展诊断实验,并与CNN、堆叠降噪自编码器(Stacked Denoise AutoEncoder,SDAE)两种深度学习方法进行对比,结果表明,该方法在高噪声环境下具有更高的故障识别率。     

Automatic vision-based grain optimization and analysis of multi-crystalline solar wafers using hierarchical region growing

Solar power has become an attractive alternative source of energy. The multi-crystalline solar cell has been widely accepted in the market because it has a relatively low manufacturing cost. Multi-crystalline solar wafers with larger grain sizes and fewer grain boundaries are higher quality and convert energy more efficiently than mono-crystalline solar cells. In this article, a new image processing method is proposed for assessing the wafer quality. An adaptive segmentation algorithm based on region growing is developed to separate the closed regions of individual grains. Using the proposed method, the shape and size of each grain in the wafer image can be precisely evaluated. Two measures of average grain size are taken from the literature and modified to estimate the average grain size. The resulting average grain size estimate dictates the quality of the crystalline solar wafers and can be considered a viable quantitative indicator of conversion efficiency.     

A novel hybrid resampling for semiconductor wafer defect bin classification

Generally, defective dies on semiconductor wafer maps tend to form spatial clusters in distinguishable patterns which contain crucial information on specific problems of equipment or process, thus it is highly important to identify and classify diverse defect patterns accurately. However, in practice, there exists a serious class imbalance problem, that is, the number of the defective dies on semiconductor wafer maps is usually much smaller than that of the non-defective dies. In various machine learning applications, a typical classification algorithm is, however, developed under the assumption that the number of instances for each class is nearly balanced. If the conventional classification algorithm is applied to a class imbalanced dataset, it may lead to incorrect classification results and degrade the reliability of the classification algorithm. In this research, we consider the semiconductor wafer defect bin data combined with wafer warpage information and propose a new hybrid resampling algorithm to improve performance of classifiers. From the experimental analysis, we show that the proposed algorithm provides better classification performance compared to other data preprocessing methods regardless of classification models.     

A Method for Improving CNN-Based Image Recognition Using DCGAN

Image recognition has always been a hot research topic in the scientific community and industry. The emergence of convolutional neural networks(CNN) has made this technology turned into research focus on the field of computer vision, especially in image recognition. But it makes the recognition result largely dependent on the number and quality of training samples. Recently, DCGAN has become a frontier method for generating images, sounds, and videos. In this paper, DCGAN is used to generate sample that is difficult to collect and proposed an efficient design method of generating model. We combine DCGAN with CNN for the second time. Use DCGAN to generate samples and training in image recognition model, which based by CNN. This method can enhance the classification model and effectively improve the accuracy of image recognition. In the experiment, we used the radar profile as dataset for 4 categories and achieved satisfactory classification performance. This paper applies image recognition technology to the meteorological field.     

Visualization for Explanation of Deep Learning-Based Defect Detection Model Using Class Activation Map

Recently, convolutional neural network (CNN)-based visual inspection has been developed to detect defects on building surfaces automatically. The CNN model demonstrates remarkable accuracy in image data analysis; however, the predicted results have uncertainty in providing accurate information to users because of the “black box” problem in the deep learning model. Therefore, this study proposes a visual explanation method to overcome the uncertainty limitation of CNN-based defect identification. The visual representative gradient-weights class activation mapping (Grad-CAM) method is adopted to provide visually explainable information. A visualizing evaluation index is proposed to quantitatively analyze visual representations; this index reflects a rough estimate of the concordance rate between the visualized heat map and intended defects. In addition, an ablation study, adopting three-branch combinations with the VGG16, is implemented to identify performance variations by visualizing predicted results. Experiments reveal that the proposed model, combined with hybrid pooling, batch normalization, and multi-attention modules, achieves the best performance with an accuracy of 97.77%, corresponding to an improvement of 2.49% compared with the baseline model. Consequently, this study demonstrates that reliable results from an automatic defect classification model can be provided to an inspector through the visual representation of the predicted results using CNN models.     

Detection and classification of defect patterns on semiconductor wafers

The detection of process problems and parameter drift at an early stage is crucial to successful semiconductor manufacture. The defect patterns on the wafer can act as an important source of information for quality engineers allowing them to isolate production problems. Traditionally, defect recognition is performed by quality engineers using a scanning electron microscope. This manual approach is not only expensive and time consuming but also it leads to high misidentification levels. In this paper, an automatic approach consisting of a spatial filter, a classification module and an estimation module is proposed to validate both real and simulated data. Experimental results show that three types of typical defect patterns: (i) a linear scratch; (ii) a circular ring; and (iii) an elliptical zone can be successfully extracted and classified. A Gaussian EM algorithm is used to estimate the elliptic and linear patterns, and a spherical-shell algorithm is used to estimate ring patterns. Furthermore, both convex and nonconvex defect patterns can be simultaneously recognized via a hybrid clustering method. The proposed method has the potential to be applied to other industries.     

基于卷积神经网络的印刷品颜色缺陷检测

目的 提取样本图像颜色直方图特征对卷积神经网络进行训练,达到快速、高准确率检测图像颜色缺陷的目的.方法 将标准图像从RGB颜色空间转换至HSV颜色空间,通过改变图像H,S,V三分量值获取训练样本和测试样本;在HSV颜色空间中非均匀量化图像的颜色直方图,得到所有训练样本和测试样本的颜色直方图特征;利用样本图像颜色直方图特征训练卷积神经网络,然后对测试样本进行检测,研究检测的速度、准确率,并将该检测方法与逐像素、超像素、BP神经网络和支持向量机方法进行对比.结果 对于图片尺寸为512×512的彩色图像,卷积神经网络检测单幅图片的平均检测时间约为57.66 ms,训练样本图像为50000张时,卷积神经网络方法对10000张测试样本进行检测的准确率为99.77％.结论 卷积神经网络方法在保证高准确率的前提下大幅提高检测精度,对于印刷品色差缺陷在线检测具有良好的应用价值.     

硅及硅基半导体材料中杂质缺陷和表面的研究

随着超大规模集成电路设计线宽向深亚微米级（<0.5μm）和亚四分之一微米级（<0.25μm）发展,对半导体硅片及其它硅基材料的质量要求越来越高,研究上述材料中各种杂质的行为,控制缺陷类型及数量,提高晶体完整性,降低表面污染和采用缺陷工程的方法改善材料质量显得尤为重要。文章阐述了深亚微米级和亚四分之一微米级集成电路用大直径硅材料中铁、铜金属和氧、氢、氮非金属杂质元素的行为,点缺陷及其衍生缺陷的本质与控制方法,硅片表面形貌、表面污染与检测方法的研究热点。同时还介绍了外延硅、锗硅及绝缘体上硅（SOI）等硅基材料的特性、制备及工艺技术发展趋势,展望了跨世纪期间硅及硅基材料产业发展的技术经济前景。     

Effect of Pre-heat and Inert Gas Species on Cryogenic Aerosol Cleaning Performance in Semiconductor Manufacturing

Cryogenic aerosol cleaning is a dry cleaning method used in the back end of line (BEOL) semiconductor manufacturing to remove defects from planar hydrophobic surfaces such as SiCOH and SiCxNyHz. Cryogenic aerosol cleaning is preferred over conventional wet cleaning methods as it is a non-contact cleaning method, which uses inert gases to generate sub-micrometer-sized solid aerosol particles that physically remove nanometer-sized contaminants on wafer surfaces. Particle removal mechanism involves detachment of the particles upon impact with aerosol, diffusion, and finally entrainment away from the wafer. In BEOL metal line patterning, particles on the dielectric isolation surfaces translate through the subsequent lithography and copper fill steps in to single or multiple metal line open defects that are yield killers. In this study, we show that the particle removal performance of the standard aerosol cleaning can be enhanced by pre-heating the wafer and use of a higher molecular weight inert gas, namely Ar, for aerosol generation. Both the addition of a Pre-heat step and the use of Ar as the aerosol source showed 47–52% reduction in single and multiple line opens detected through wafer electrical tests during high volume semiconductor manufacturing process.