Fine grinding of silicon wafers: designed experiments

Silicon wafers are the most widely used substrates for semiconductors. The falling price of silicon wafers has created tremendous pressure to develop cost-effective processes to manufacture silicon wafers. Fine grinding possesses great potential to reduce the overall cost for manufacturing silicon wafers. The uniqueness and the special requirements of fine grinding have been discussed in a paper published earlier in this journal. As a follow-up, this paper presents the results of a designed experimental investigation into fine grinding of silicon wafers. In this investigation, a three-variable two-level full factorial design is employed to reveal the main effects as well as the interaction effects of three process parameters (wheel rotational speed, chuck rotational speed and feed-rate). The process outputs studied include grinding force, spindle motor current, cycle time, surface roughness and grinding marks.     

Grinding induced subsurface cracks in silicon wafers

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. To ensure high surface quality, the damage layer generated by each of the machining processes (such as lapping and grinding) has to be removed by its subsequent processes. Therefore it is essential to assess the subsurface damage for each machining process. This paper presents the observation of subsurface cracks in silicon wafers machined by surface grinding process. Based on cross-sectional microscopy methods, several crack configurations are identified. Samples taken from different locations on the wafers are examined to investigate the effects of sample location on crack depth. The effects of grinding parameters such as feedrate and wheel rotational speed on the depth of subsurface crack have been studied by a set of factorial design experiments. Furthermore, the relation between the depth of subsurface crack and the wheel grit size is experimentally determined.     

Fine grinding of silicon wafers

Silicon wafers are used for the production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. As one of such processes, surface grinding of silicon wafers has attracted attention among various investigators and a limited number of articles can be found in the literature. However, no published articles are available regarding fine grinding of silicon wafers. In this paper, the uniqueness and the special requirements of the silicon wafer fine grinding process are introduced first. Then some experimental results on the fine grinding of silicon wafers are presented and discussed. Tests on different grinding wheels demonstrate the importance of choosing the correct wheel and an illustration of the proper selection of process parameters is included. Also discussed are the effects of the nozzle position and the flow rate of the grinding coolant.     

Origin,modeling and suppression of grinding marks in ultra precision grinding of silicon wafers

A phenomenon commonly encountered in grinding of silicon wafers is the grinding marks, which are difficult to remove by subsequent polishing process, and have been a great obstacle to the manufacture of silicon wafers with higher flatness. In this paper, the grinding marks formation mechanism was clarified, a grinding marks formation model and an angular wavelength model were developed, and a grinding marks suppression method was proposed. A series of grinding experiments were carried out to verify the developed models and investigate the effect of the wafer rotational speed, the wheel rotational speed, the infeed rate, the axial run out of the cup wheel and the spark out time. The results show that: (1) grinding marks are waviness generated on silicon wafers caused by non-uniform material removal circumferentially due to the axial run out of the cup wheel; (2) grinding marks present multiple angular wavelengths characteristics; (3) the angular wavelength of grinding marks is a one-variable function of the rotational speed ratio of the wheel to the wafer; and (4) grinding marks could be suppressed significantly by properly selecting the rotational speed ratio.     

Fine grinding of silicon wafers: a mathematical model for grinding marks

The majority of today’s integrated circuits are constructed on silicon wafers. Fine-grinding process has great potential to improve wafer quality at a low cost. Three papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third paper developed a mathematical model for the chuck shape, addressing one of the technical barriers that have hindered the widespread application of this technology: difficulty and uncertainty in chuck preparation. As a follow up, this paper addresses another technical barrier: lack of understanding on grinding marks. A mathematical model to predict the locus of the grinding lines and the distance between two adjacent grinding lines is first developed. With the developed model, the relationships between grinding marks and various process parameters (wheel rotational speed, chuck rotational speed, and wheel diameter) are then discussed. Finally, results of pilot experiments to verify the model are discussed.     

Waviness removal in grinding of wire-sawn silicon wafers: 3D finite element analysis with designed experiments

Silicon wafers are used to fabricate more than 90% of integrated circuits. Surface grinding has been used to flatten wire-sawn silicon wafers. A major issue in grinding of wire-sawn wafers is that conventional grinding cannot effectively remove the waviness induced by wire-sawing process. Soft-pad grinding is a promising method to effectively remove waviness. This paper presents the results of three-dimensional (3D) finite element analysis of soft-pad grinding of wire-sawn silicon wafers. In this investigation, a four-factor two-level full factorial design is employed to reveal main effects as well as interaction effects of four factors (Young’s modulus, Poisson’s ratio, and thickness of the soft pad, and waviness wavelength of the wafer) on the effectiveness of waviness reduction. Implications of this study to manufacturing are also discussed.     

Defect-free Fabrication for Single Crystal Silicon Substrate by Chemo-Mechanical Grinding

IC chips are built on Si substrates which must have a high degree of crystalline perfection. The single crystal Si ingot is first sawn into wafers, each of which then undergoes lapping, etching and several steps of polishing to remove the mechanical imperfection and to achieve mirror surfaces. An alternative process has been newly developed by effective use of solid-state reaction between the CeO₂ abrasives and Si. Si is removed in a form of amorphous Ce-O-Si at a dry condition. The fabricated ?300 mm Si wafers are examined on both surface and subsurface. The results show that 1) the surface is generated by fixed abrasives following grinding dynamics, 2) no defect or mechanical (structural) imperfection is introduced during fabrication and 3) far better quality is achieved than that by CMP.     

Finite element analysis for grinding of wire-sawn silicon wafers: a designed experiment

Silicon is the primary semiconductor material used to fabricate microchips. The quality of microchips depends directly on the quality of starting silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Surface grinding is one of the processes used to flatten the wire-sawn wafers. A major issue in grinding of wire-sawn wafers is the reduction and elimination of wire-sawing induced waviness. This paper presents the results of a finite element analysis for grinding of wire-sawn silicon wafers. In this investigation, a four-factor two-level full factorial design is employed to reveal the main effects as well as the interaction effects of four factors (wafer thickness, waviness wavelength, waviness height and grinding force) on effectiveness of waviness reduction. The implications of this study to manufacturing are also discussed.     

An experimental investigation into soft-pad grinding of wire-sawn silicon wafers

Silicon is the primary semiconductor material used to fabricate microchips. A series of processes are required to manufacture high-quality silicon wafers. Surface grinding is one of the processes used to flatten wire-sawn wafers. A major issue in grinding of wire-sawn wafers is reduction and elimination of wire-sawing induced waviness. Results of finite element analysis have shown that soft-pad grinding is very effective in reducing the waviness. This paper presents an experimental investigation into soft-pad grinding of wire-sawn silicon wafers. Wire-sawn wafers from a same silicon ingot were used for the study to ensure that these wafers have similar waviness. These wafers were ground using two different soft pads. As a comparison, some wafers were also ground on a rigid chuck. Effectiveness of soft-pad grinding in removing waviness has been clearly demonstrated.     

Fine grinding of silicon wafers: effects of chuck shape on grinding marks

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon ingot into wafers. With continuing shrinkage of feature sizes of microchips, more stringent requirement is imposed on wafer flatness. Fine grinding of silicon wafers is a patented technology to produce super flat wafers at a low cost. Six papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented the mathematical models for the chuck shape and the grinding marks, respectively. The fifth paper developed a mathematical model for the wafer shape and the sixth paper studied machine configurations for spindle angle adjustments. This paper is a follow up of the above-mentioned work. A mathematical model to predict the depth of grinding marks for any chuck shape will be first developed. With the developed model, effects of the chuck shape (as well as the wheel radius) on the depth of grinding marks will be studied. Finally, results of pilot experiments to verify the model will be discussed.     

Grinding wheels for manufacturing of silicon wafers: A literature review

Grinding is an important process for manufacturing of silicon wafers. The demand for silicon wafers with better quality and lower price presents tremendous challenges for the grinding wheels used in the silicon wafer industry. The stringent requirements for these grinding wheels include low damage on ground surfaces, self-dressing ability, consistent performance, long wheel lives, and low prices. This paper presents a literature review on grinding wheels for manufacturing of silicon wafers. It discusses recent development in abrasives, bond materials, porosity formation, and geometry design of the grinding wheels to meet the stringent requirements.     

Simultaneous double side grinding of silicon wafers: a literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits (ICs). The quality of ICs depends directly on the quality of silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Simultaneous double side grinding (SDSG) is one of the processes to flatten the wire-sawn wafers. This paper reviews the literature on SDSG of silicon wafers, covering the history, machine development (including machine configuration, drive and support systems, and control system), and process modeling (including grinding marks and wafer shape). It also discusses some possible topics for future research.     

A grinding-based manufacturing method for silicon wafers: generation mechanisms of central dimples on ground wafers

Silicon wafers are the fundamental building blocks for most integrated circuits. The lapping-based manufacturing method currently used to manufacture the majority of silicon wafers will not be able to meet the ever-increasing demand for flatter wafers and lower prices. A grinding-based manufacturing method has been investigated experimentally to demonstrate its potential to manufacture flat silicon wafers at a lower cost. It has been demonstrated that the site flatness on the ground wafers (except for a few sites at the wafer center) could meet the stringent specifications for future silicon wafers. This paper, as a follow up, addresses one of the reasons for the poor flatness at the wafer center: central dimples on ground wafers. A finite element model is developed to illustrate the generation mechanisms of central dimples. Then, effects of influencing factors (including Young's modulus and Poisson's ratio of the grinding wheel segment, dimensions of the wheel segment, grinding force, and chuck shape) on the central dimple sizes are studied. Pilot experimental results will be presented to substantiate the predicted results from the finite element model. This provides practical guidance to eliminate or reduce central dimples on ground wafers.     

ELID grinding of silicon wafers: A literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits. There have been continuous demands for higher quality silicon wafers with lower prices, and it becomes more and more difficult to meet these demands using current manufacturing processes. In recent years, research has been done on electrolytic in-process dressing (ELID) grinding of silicon wafers to explore its potential to become a viable manufacturing process. This paper reviews the literature on ELID grinding, covering its set-ups, wheel dressing mechanism, and experimental results. It also discusses the technical barriers that have to be overcome before ELID grinding can be used in manufacturing.     

Precision machining of small holes by the hybrid process of electrochemical removal and grinding

This paper presents a hybrid process of grinding and electrochemical removal for machining of precision small holes with hard-to-machine materials. In the process, a metal rod with coated abrasives as cathode tool rotates at high speed and removes material electrochemically and mechanically for a pre-machined pilot hole. The effects of process parameters on the hole surface quality and dimensional accuracy were demonstrated experimentally. Material removals on grinding and electrochemical machining are well balanced by rationally determining machining voltage, tool rotation speed and feed rate. Precision holes of diameters down to 0.6 mm with sharp edges and without burrs have been produced.     

An experimental study of flat fixed abrasive grinding of silicon wafers using resin-bonded diamond pellets

The purpose of this paper is to investigate the effect of the diamond grain size, the wheel rotation speed, the table rotation speed, and the applied pressure in the vertical flat grinding on the surface roughness of silicon wafers using Taguchi orthogonal array design. Besides, the pits and resistivity on the wafers were studied as well. The experiment results showed that the diamond grain size and the wheel rotation speed of the vertical flat grinding for the roughness of wafers obtained are the relatively larger significant contribution. When the smaller diamond grit size, the faster wheel rotation speed, the faster table rotation speed, and the smaller applied pressure in the flat grinding are employed, the traces produced by the grains are denser and the chip thickness and the depth of cut were smaller, which cause the silicon wafer to produce the higher degree of the ductile grinding. This will lead the wafer surface to produce the smaller amount and size of the pits, thereby generating the lower surface roughness. In addition, the center site of the wafer obtained is the smaller amount and size of the pits than the outer of the wafer, which produces the better surface roughness and the lower resistivity.     

Fine grinding of silicon wafers: a mathematical model for the wafer shape

Over 90% of semiconductors are built on silicon wafers. The fine grinding process has great potential to produce very flat wafers at a low cost. Four papers on fine grinding have been previously published by the authors. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented mathematical models for the chuck shape and the grinding marks, respectively. As a follow up, this paper develops a mathematical model for the wafer shape. After the model is described, its practical applications in wafer manufacturing are discussed.     

Development of a Dicing Blade With Photopolymerizable Resins for Improving Machinability

Dicing blades are widely used for the cutting of hard-brittle materials such as ceramics, glass, and quartz. Thermosetting resin is effective as a bonding agent in conventional blades. For production, it takes several hours for heat curing by the hot press method and a lapping process is also required for truing the blade flatness. These result in blades with high cost. In this paper, the application of photopolymerizable resin to the blade is proposed, for the purpose of reducing production costs and improving machinability. Four types of blade (a single layered, a three layered, a slotted and a slot-filled blade) were used. As the result of a series of cutting tests on silicon wafers, in comparison with the thermoset resin blade, the grinding ratio, the spindle motor current and the chipping size distribution on the workpiece surface, have been improved.     

Grinding of silicon wafers using an ultrafine diamond wheel of a hybrid bond material

An ultrafine diamond wheel of a mesh size of 12,000 was fabricated by using a hybrid bond material, which consists of silicon carbide, silica and alumina. The employment of the newly developed wheel enabled excellent performance during grinding of silicon wafers. An extremely smooth surface of an average roughness of 0.6 nm was achieved. TEM examinations showed that the total thickness of the defected layer was less than 60 nm.     

离心铸球工艺研究

介绍了离心铸造磨球的工艺,以及转速、内浇口断面积计算方法和影响工艺过程的因素。在离心铸球工艺中,可应用有效重度和等效压头原理计算转速和内浇口断面积。转速在５００～７００ｒ／ｍｉｎ和每个内浇口面积不小于０．４ｃｍ２时,铸球内部晶粒度达到６～７级,硬度值分布均匀。同时分析了在旋转的浇注系统中,金属液运动的规律。