Simulink behavioral modeling of a 10-bit pipelined ADC

The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters (ADCs). All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages). Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements.     

软件无线电直接射频采样的低速高效ADC系统研究

本文提出了一种低速高效混合滤波器组ADC系统，该ADC系统能对射频模拟信号（2MHz-2000MHz)直接进行模／数转换，而且分辨率达到14比特以上，但其数字信号输出速率才105MSPS，因而该低速高效混合滤波器组ADC系统对软件无线电的直接射频采样有很高的实用价值。     

STD工控机电气成套装置的应用与升级

总结了用STD总线工业控制计算机(以下简称为STD工控机)构成的电气自动化成套装置在研制、开发及现场实际商业运行期所积累的经验,并根据市场预测以及目前工控机发展动态,结合微机继电保护的开发,提出了电气自动化成套装置设计的最佳解决方案.     

MASH ΣΔ modulators with a noise-shaped two-step ADC in the second stage

In this paper, a multi-stage noise-shaping (MASH) sigma-delta (ΣΔ) modulator is proposed to be used in low oversampling ratio (OSR) applications. It utilizes a noise-shaped two-step (NSTS) analog-to-digital converter (ADC) in the second stage and benefits its inter-stage gain to provide an extra attenuation of the quantization noise such that the same specifications of a traditional modulator are achieved but with a lower order of noise-shaping. Furthermore, large number of bits is resolved in the second stage while equal number of comparators is used. Compared to the single-loop NSTS ADC, in the proposed structure, the complexity problem of the feedback path and coefficient spreading are eliminated. As an example, a MASH 2-1 sigma-delta modulator has been designed and simulated in a 90 nm CMOS process using Spectre. The achieved resolution is 13.44 effective number of bits in 6.25 MHz signal bandwidth while consuming 19.6 mW power from a single 1 V supply. The sampling frequency is 100 MHz and the simulated figure of merit is 141 fJ/conv-step which shows the efficiency of the proposed modulator.     

A pseudo‐differential current‐reuse structure for opamp‐sharing pipelined analog‐to‐digital converters

In this paper, a power efficient pseudo‐differential (PD) current‐reuse structure is presented to alleviate the memory effects of opamp‐sharing in pipelined analog‐to‐digital converters. To implement the PD current‐reuse structure, a switched‐capacitor circuit is introduced for multiplying digital‐to‐analog converter, which has a slight modification compared with the conventional switching scheme with no power penalty. In the proposed multiplying digital‐to‐analog converter circuit, the common‐mode offset amplification of the PD structures is eliminated. Moreover, a PD current‐reuse amplifier is developed from the telescopic structure with an inverter‐based gain‐boosting circuit. The effectiveness of the proposed structure is evaluated in comparison with existing current‐reuse techniques. Copyright © 2014 John Wiley & Sons, Ltd.     

软件无线电的直接射频采样ADC系统研究

提出了一种高速混合滤波器组ADC系统，该ADC系统能对射频模拟信号(2MHz～2000MHz)直接进行模／数转换，而且分辨率达到12比特以上。显然，用此高速混合滤波器组ADC系统可以完成软件无线电的直接射频采样．     

Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder

This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15-bit resolution (74 dB-Signal-to-noise plus Distortion Ratio [SNDR]). A self-repairing (SR) thermometer-to-binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one-half least-significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15-bit pipeline ADC using a novel calibrated dynamic-latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications.     

Shifting the sampled input signal in successive approximation register analog-to-digital converters to reduce the digital-to-analog converter switching energy and area

In this paper, a switching scheme is presented to reduce the capacitive digital-to-analog converter (DAC) switching energy, area, and the number of switches in successive approximation register (SAR) analog-to-digital converters (ADCs). In the proposed DAC switching method, after a few most significant bits (MSBs) decision, the sampled differential input signal is shifted into two special regions where the required DAC switching energy and area is less than the other regions. This technique can be utilized in most of the previously reported DAC switching schemes to further reduce the capacitive DAC switching energy and area. The conventional and two recently presented DAC switching techniques are utilized in the proposed SAR ADC to evaluate its usefulness.     

Research progress of time-interleaved analog-to-digital converters

Channel mismatch calibration techniques of time-interleaved analog-to-digital converters (TI-ADCs) are reviewed. The research on sampling technology of TI-ADCs is introduced, and the influence mechanism of channel mismatch has been analyzed briefly. Subsequently, the latest research progress of the domestic and foreign error calibration techniques of TI-ADCs is elaborated. The implementation methods, advantages and disadvantages of each calibration technique have been summarized, existing problems are analyzed. Finally, future development trends are prospected. These works could provide a reference for advancing the research field.     

A data optimization test technique for characterizing embedded ADCs

A novel data optimization test technique is presented which utilizes a BIST structure, an ADC model and histogram data to characterize embedded ADCs. A practical 8 bit ADC is modeled and then characterized using 20% less data points then conventional analysis with a 78% reduction in the amount of data required to be shifted off-chip. Comparisons between theoretical, modeled and practical results are also made in the paper.