最坏情况下X3SAT最大海明距离问题最小上界

X3SAT最大海明距离问题是指对于一个X3SAT问题实例,寻找该问题的任意两组可满足赋值之间的最大海明距离。提出了一个基于DPLL的精确算法HMX来求解X3SAT最大海明距离问题,根据公式中某个变量在两组真值赋值中的不同取值进行分支。给出了多种化简规则,这些规则很好地提高了算法的时间效率。证明了该算法可以将X3SAT最大海明距离问题的最小上界由目前最好的O(1.7107n)缩小到O(1.6760n),其中n为公式中变量的数目。     

Blind estimation of the PN sequence in lower SNR DS-SS signals with residual carrier

This paper presents a method of singular value decomposition (SVD) plus digital phase lock loop (DPLL) to solve the difficult problem of blind pseudo-noise (PN) sequence estimation in low signal to noise ratios (SNR) direct sequence spread spectrum (DS-SS, DS) signals with residual carrier. Of course, the method needs to know the parameters of DS signal, such as the period and code rate of PN sequence. Firstly, the received signal is sampled and divided into non-overlapping signal vectors according to a temporal window, whose duration is two periods of PN sequence. Then, an autocorrelation matrix is computed and accumulated by the signal vectors one by one. The PN sequence with residual carrier can be estimated by the principal eigenvector of this autocorrelation matrix. Furthermore, a DPLL is used to deal with the estimated PN sequence with residual carrier, it estimates and tracks the residual carrier, removes the residual carrier in the end. Theory analysis and computer simulation results show that this method can effectively realize the PN sequence estimation from the input DS signals with residual carrier in lower SNR.     

一次性求解多个SAT问题

在实际应用中通常需要求解对应CNF（ConjunctiveNormalForm）公式之间仅相差几个子句的一系列SAT（SatisfiabilityProblem）问题,但目前绝大多数SAT求解算法都是针对单一SAT问题设计的。为此,基于DPLL提出了nDPLL算法,并在随机问题上对该算法的效率进行测试。实验结果表明,nDPLL算法能一次性求解多个SAT问题,对于特定范围的CNF公式集具有较高的效率,CNF公式集的规模越大、相近因子越高、子句数和变量数的比值越大,则nDPLL算法的效率越高。     

基于FPGA硬件实现的谐波检测方法

针对现有系统对谐波检测实时性差和精度低的问题,介绍一种基于傅立叶变换和FPGA硬件实现的谐波检测方法.分析了谐波检测中影响测量精度的关键因素,采用数字锁相环来同步被测信号,以减小由非同步采样所产生的误差.基-4FFT 处理器的硬件设计采用全并行的乘法运算单元结构和并行的存储分配方法,最大限度地提高谐波检测的速度.数字锁相环和基-4 FFT 算法用VHDL语言设计实现,并用MAX plus Ⅱ软件进行仿真,仿真结果表明,所设计的数字锁相环可以很好地跟踪被测信号,在180ms时,误差仅为0.01Hz,很好地消除了非同步采样所引起的测量误差;采用所设计的基-4FFT运算器对给定的谐波数据进行运算,得到的谐波幅值和相位误差小于0.05%,运算时间仅为8μs.     

中低轨卫星多普勒数据处理技术研究

分析了中低轨卫星多普勒频率模型特性,采用数据拟合法对多普勒数据进行处理,有效抑制随机误差。仿真结果表明,经过处理后的观测数据精度得到了明显提高。     

动静态结合排序决策的可满足性问题解决器

采用冲突驱动回溯、两观察变量法等思想,静态分析和动态更新相结合的排序决策,鼓励冲突,尽早剪除不满足解空间,提高算法速度.根据变量正反文字出现次数的乘积进行初始排序,优先考虑正反文字出现次数较多变量的赋值;采用冲突驱动、动态更新变量顺序、优先考虑发生冲突子句中变量的赋值,尽可能避免当前冲突.实验结果表明：与采用其他决策策略的解决器相比,文中的解决器拥有一定的速度优势.     

基于FPGA的线性可变码位控制全数字锁相环的设计与仿真

线性可变码位控制全数字锁相环（LVBC－DPLL）具有环路捕捉时间快的特点，该文介绍了以EDA技术作为开发手段的LVBC－DPLL的设计与实现，并分析了系统的稳态性能及仿真结果。     

基于DSP实现感应加热数字锁相环的研究

介绍了在感应加热电源中采用DSP实现频率跟踪的数字锁相环(DPLL)方法,给出了实现该锁相环的算法及其数学模型,实验结果验证了该方法的可行性。     

An effective approach for parameter determination of the digital phase-locked loop in the z-domain

In digital communication systems, typical methodologies in determining loop parameters of the digital phase-locked loop (DPLL) are based on the mapping transformation from the analog domain to the digital domain. However, such transform based algorithms are relatively complicated and not straightforward, and they also cause the problem that loop parameters are affected by the pre-detection integration time greatly. To solve these issues, an effective direct method of determining loop parameters of the second-order DPLL in the z-domain is proposed in this paper. Through ascertaining specific positions of the closed-loop system function's poles inside the right-hand side of the z-plane's unit circle, unknown parameters are calculated directly and flexibly in this method, which enables the DPLL to acquire good low-pass filtering characteristic and system stability. This novel method not only reduces the complexity of solving the parameters, but also eliminates the effect of the pre-detection integration time on loop parameters. Simulation results are provided to confirm the feasibility of the proposed method and to show that the DPLL obtained by this method achieves the similar tracking performance to the discretized PLL.