Compact modeling of amorphous‐silicon thin‐film transistors with BSIM3

Abstract— A novel approach of modeling a‐Si:H TFTs with the industry‐standard BSIM3 compact model is presented. The described approach defines the a‐Si:H TFT drain current and terminal charges as explicit functions of terminal voltages using a minimum set of BSIM3 parameters. The set of BSIM3 parameters is chosen based on the electrical and physical characteristics of the a‐Si:H TFT and their values extracted from measured data. By using the selected BSIM3 model parameters, the a‐Si:H TFT is simulated inside SPICE to fit the simulated I‐V and C‐V curves with the measured results. Finally, the extracted BSIM3 model is validated by simulating the kickback voltage effect in an AMLCD pixel array.     

济钢低碳低硅钢冶炼工艺的开发与应用

介绍了济钢第三炼钢厂采用转炉-LF精炼-ASP薄板坯连铸生产低碳低硅钢的工艺实践。通过提高转炉终点命中率防止钢水过氧化,采取合适的钙铝比、强化连铸保护浇注等措施,解决了低碳低硅钢的钢水可浇注性问题;采取减少转炉下渣、控制加铝和精炼时间,减少了钢水回硅。批量生产08Al、SPCC低硅钢4.22t,统计分析表明,铸坯成分内控合格率为91.38%,综合合格率为99.8%。     

一种应用于流水折叠式A/D转换器的失调抵消预放大器

根据流水折叠式A/D转换器的应用要求,设计了一种失调抵消预放大器.采用开关电容电路实现失调存储技术,以减小输入失调电压对转换精度的影响,并通过引入MOS电容实现回馈噪声中和技术.基于SMIC 0.18μm CMOS工艺,在1.8V电源电压、200MHz时钟频率下,对所设计的预放大器进行了功能验证和蒙特卡洛分析.其失调方差仅为3.24mV,功耗为362μW.测试了整个10位100MS/s A/D转换器,最大INL和DNL分别为1.6LSB和0.6LSB.在fin=32MHz,fs=100MHz时,测得SFDR为55dB.     

改善a—SiTFTLCD像素电极跳变电压方法研究

非晶硅薄膜晶体管液晶显示器（a—SiTFTLCD）中,在栅极信号由开启到关断的瞬间,由于栅源耦合电容Cgs的存在．使像素电极电压出现跳变,跳变前后像素电极电压差称为△Vp。降低△Vp一方面能减小闪烁程度,降低残像残留．同时还能最大程度地提高像素电极保持阶段的电压。防止出现因TFT漏电流过大而造成的像素电极电压衰变到所应显示灰度电压之下,从而出现显示灰阶的变化。本文从理论上分析了△Vp形成原理,介绍了两种能有效降低△Vp的方法．即多栅极电路和脉冲式存储电容。     

低功耗高速流水线ADC中低回踢噪声动态比较器设计

动态比较器是低功耗高速流水线ADC的重要模块,其回踢噪声会严重影响ADC的性能.为了满足低功耗高速流水线ADC的应用需求,设计了一种全差分结构的动态比较器,具有零静态功耗、速度快、阈值电压可调等特点.中和技术的应用可以显著降低回踢噪声.电路使用TSMC 0.18 μmCMOS工艺,在1.8 V电源电压和100 MHz工作频率下,仿真显示回踢噪声被明显抑制,减小了75.5%.     

基于参考通道随机化的TIADC校准算法

提出了一种针对时间交织模数转换器(time interleaved ADC,TI-ADC)通道间失配误差的基于参考通道的后台校准算法。该算法利用参考通道与同采样时刻TI-ADC子通道ADC输出差值估计待校准子ADC的失配误差,然后从系统输出中减之实现自适应误差补偿;为了克服当TI-ADC系统前端不存在单独输入缓冲器时,参考ADC通过输入网络耦合对TI-ADC产生干扰问题,进一步加入随机化技术,减少残余失配误差产生毛刺;该校准系统可以实现3种主要失配误差的同时有效校准,对输入信号带宽没有限制。应用于12位1 GS/s TI-ADC系统,当输入信号频率为470 MHz时,FPGA验证结果表明,校准后无杂散动态范围(SFDR)提升了44.14 dB,达到76.16 dB。     

An 8 bit 1 MS/s SAR ADC with 7.72-ENOB

This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18 μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μ W with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.