MTJ MRAM的特性分析与设计

对 MTJ(磁隧道结 )的 GMR(巨磁阻 )效应进行了分析。 MTJ的结构、形态和工作条件会对 GMR效应产生不同的影响。提出了一种 4× 1位 MTJMRAM(磁存储器 )的电路结构 ,每个 MRAM的存储单元由一个MTJ和一个 MOSFET构成 ,用 MTJ两磁极磁化方向的相对取向表示所存储的数据 ,数字线和位线电流产生磁场的共同作用可完成 MRAM数据的写入。     

乘积合并接收的差分跳频通信系统在瑞利衰落信道上抗多音干扰的性能分析

在瑞利衰落信道上,在多音干扰和加性高斯白噪声共存的条件下,对采用乘积合并接收(PCR)方法的差分跳频(DFH)通信系统的误符号性能进行了理论分析.为验证理论分析的正确性,进行了相应的计算机仿真,将采用 PCR 方法的误符号性能与采用线性合并接收(LCR)方法的误符号性能作了比较.结果证实,在瑞利衰落信道上,DFH 通信系统采用乘积合并接收的方法要比采用 LCR 方法具有更好的抗多音干扰的性能.     

A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications

Powering billions of devices is one of the most challenging barrier in achieving the future vision of IoT. Most of the sensor nodes for IoT based systems depend on battery as their power source and therefore fail to meet the design goals of lifetime power supply, cost, reliable sensing and transmission. Energy harvesting has the potential to supplant batteries and thus prevents frequent battery replacement. However, energy autonomous systems suffer from sudden power variations due to change in external natural sources and results in loss of data. The memory system is a main component which can improve or decrease performance dramatically. The latest versions of many computing system use chip multiprocessor (CMP) with on-chip cache memory organized as array of SRAM cell. In this paper, we outline the challenges involved with the efficient power supply causing power outage in energy autonomous/self-powered systems. Also, various techniques both at circuit level and system level are discussed which ensures reliable operation of IoT device during power failure. We review the emerging non-volatile memories and explore the possibility of integrating STT-MTJ as prospective candidate for low power solution to energy harvesting based IoT applications. An ultra-low power hybrid NV-SRAM cell is designed by integrating MTJ in the conventional 6T SRAM cell. The proposed LP8T2MTJ NV-SRAM cell is then analyzed using multiple key performance parameters including read/write energies, backup/restore energies, access times and noise margins. The proposed LP8T2MTJ cell is compared to conventional 6T SRAM counterpart indicating similar read and write performance. Also, comparison with the existing MTJ based NV-SRAM cells show 51–78% reduction in backup energy and 42–70% reduction in restore energy.     

Ultra-thin dielectric breakdown in devices and circuits: A brief review

Time-dependent dielectric breakdown (TDDB), in which the traps in oxide bulk form a conducting path under application of stress voltage for long period of time, has emerged as one of the important sources of performance degradation in advanced devices. In this paper, we give an overview of the recent progress in the understanding of ultra-thin dielectric breakdown in devices and consider its impact at the circuit-level. From the device point of view, the breakdown (BD) phenomenon, including the BD statistics, trap generation models, and BD evolution in ultra-thin dielectric are presented followed by the recent studies on TDDB in high-k metal gate (HKMG) devices and magnetic tunnel junction (MTJ) memories. On the circuit side, we explore methodologies for circuit lifetime assessment, the impact of TDDB on circuit performance degradation, and design techniques to improve circuit reliability.     

JTIDS数据链在多音干扰下经过莱斯衰落信道的传输性能分析

联合战术信息分发系统(joint tactical information distribution system,JTIDS)采用软扩频、跳频、纠错编码相结合的抗干扰体制,具备很强的抗干扰能力。通过已公开的JTIDS技术体制,分析了JTIDS通信链路的数学模型,在此基础上,研究并得出了采用相干解调方式JTIDS数据链在高斯白噪声干扰和人为多音干扰条件下,经过莱斯衰落信道的符号错误概率(symbol error probability,SEP),根据理论结果进行计算,并由所得计算结果分析了干扰频率点数分布以及干扰频率偏移对于JTIDS传输性能的影响,为评估JTIDS通信网络在干扰环境下的效能提供基础。     

Study on the mechanism of perpendicular magnetic anisotropy in Ta/CoFeB/MgO system

The mechanism of perpendicular magnetic anisotropy (PMA) in a MgO-based magnetic tunnel junction (MTJ) has been studied in this article. By comparing the magnetic properties and elementary composition analysis for different CoFeB-based structures, such as Ta/CoFeB/MgO, Ta/CoFeB/Ta and Ru/CoFeB/MgO structures, it is found that a certain amount of Fe-oxide existing at the interface of CoFeB/MgO is helpful to enhance the PMA and the PMA is originated from the interface of CoFeB/MgO. In addition, Ta film plays an important role to enhance the PMA in Ta/CoFeB/MgO structure.     

Structural and tunneling properties of magnetic tunnel junctions with Al-O and MgO barrier

Two types of magnetic tunnel junctions (MTJs) with the configuration: substrate Si(1 0 0)/SiO₂ 47 nm/buffer/IrMn 12 nm/CoFe 2.5 nm/Al-O 1.5 nm/NiFe 3 nm/Ta 5 nm and Si(1 0 0)/SiO₂ 47 nm/buffer/IrMn 10 nm/CoFeB 3 nm/MgO 2 nm/CoFeB 4 nm/Ta 5 nm were prepared by the sputtering technique with two different buffers: A-Cu 25 nm and B-Ta 5 nm/Cu 25 nm. The B buffer caused a high texture of MTJs whereas in the case of the A buffer junctions texture was weak. Crystallites in the textured layers grew in a columnar like shape that induced interfacial roughness. High textured buffer B caused high interfacial roughness that reduced the resistance-area (RA) product due to a barrier thickness fluctuation. RA also changed substantially depending on the type of a barrier. The highest RA product ∼15 MΩ μm² was achieved for a low textured junction with Al-O barrier whereas in the high textured MgO sample RA product was ∼100 kΩ μm². Tunnel magnetoresistance (TMR) measured at room temperature was about 45% for the samples with Al-O barrier, whereas for the samples with MgO barrier TMR was about three times higher and achieved 140%.     

Analysis of dielectric breakdown in CoFeB/MgO/CoFeB magnetic tunnel junction

The time-dependent dielectric breakdown has been investigated in a series of nominally identical Co–Fe–B/MgO/Co–Fe–B junctions by voltage ramp experiments. The results divulge that the breakdown voltage strongly depends on the polarity of the applied voltage, junction area, ramp speed and the annealing temperature. Magnetic tunnel junctions (MTJs) with positive bias on the top electrode show higher breakdown voltage than MTJs with negative bias. We found that there is a significant decrease in the breakdown voltage when the annealing temperature is increased above 350 °C. The experimental data can be described by different specific forms of breakdown probability functions which lead to different extrapolation of life time of junctions.     

采用混合MTJ/CMOS和SABL结构的密码算法电路设计

为了在提高轻量级密码算法(Lightweight cipher algorithm, LWCA)电路安全性的同时降低功耗,提出了一种磁隧道结(Magnetic tunnel junction, MTJ)/CMOS混合结构查找表(Look up table, LUT)电路,该结构通过与感测放大器逻辑(Sense amplifier based logic, SABL)元件配合可以实现完整的PRESENT-80加密算法电路。设计将MTJ器件引入防护电路设计中,进而提出了一种基于混合MTJ/CMOS结构的双轨查找表(Look-up table, LUT)电路结构。首先,基于40 nm CMOS工艺库和MTJ器件仿真模型,使用新提出的双轨查找表结构设计了加密算法电路工作过程中所需要的关键S-box电路并通过了仿真验证。然后,利用该电路和敏感放大器逻辑元件电路结构组合设计了PRESENT-80密码算法的完整电路。最后对所设计的电路模型进行了相关性功耗分析攻击(CPA)攻击,同时为了方便进行对比研究,还对使用传统CMOS单轨和SABL双轨结构实现的PRESENT-80加密算法电路模型进行了相同条件...     

Self-Organized Sub-bank SHE-MRAM-based LLC: An energy-efficient and variation-immune read and write architecture

In order to reduce static energy consumption, emerging Non-Volatile Memory (NVM) technologies such as Spin Transfer Torque Magnetic RAM (STT-MRAM), Spin-Hall Effect Magnetic RAM (SHE-MRAM), Phase Change Memory (PCM), and Resistive RAM (RRAM) are under intense research. Additionally, there is a demand for more reliable circuits as the technology scales due to increased error rates caused by the increased impact of Process Variation (PV). In order to combat PV-induced reliability problems, a novel approach is proposed herein that improves the reliability of read and write operations in emerging NVMs. In the proposed design, which is called the Self-Organized Sub-bank (SOS) approach, two Sense Amplifiers (SAs) have been adopted, one with improved reliability and one with improved energy efficiency profiles, in order to increase the performance of the read operation. In particular, based on the result of a Power-On Self-Test (POST), which detects PV-impact on sub-banks, SOS chooses between a reliable and an energy-efficient SA and assigns a preferred SA to each sub-bank. Furthermore, in order to increase the performance of the write operation, SHE-MRAM is replaced with STT-MRAM to provide better write energy profile. Additionally, SOS design is once implemented with a reliable write scheme and once with an energy-efficient write scheme and results are compared and analyzed. Based on the preliminary observation in our case study, 21.5% of read operations are extremely vulnerable to PV impacts. Our results indicate that the proposed SOS approach reduces the vulnerability of the read operation by 40% on average, hence reducing the fault propagation. In particular, the SOS alleviates Vulnerable False Data Sensing (VFDS) by 82% on average, while enhancing True Data Sensing (TDS) from 72.5% to 95% across all workloads studied herein compared to LLC with conventional STT-MRAM. Additionally, SOS using the reliable write circuit provides 161% improved Energy Delay Product (EDP) on average compared to SOS with conventional STT-MRAM, while providing less than 8% write current variation. On the other hand, SOS using energy-efficient write circuit offers 39% improved EDP on average compared to the SOS using reliable write circuit and 62% EDP improvement over conventional STT-MRAM.