Bayesian Inference for ARFIMA Models

This article develops practical methods for Bayesian inference in the autoregressive fractionally integrated moving average (ARFIMA) model using the exact likelihood function, any proper prior distribution, and time series that may have thousands of observations. These methods utilize sequentially adaptive Bayesian learning, a sequential Monte Carlo algorithm that can exploit massively parallel desktop computing with graphics processing units (GPUs). The article identifies and solves several problems in the computation of the likelihood function that apparently have not been addressed in the literature. Four applications illustrate the utility of the approach. The most ambitious is an ARFIMA(2,d,2) model for the Campito tree ring time series (length 5405), for which the methods developed in the article provide an essentially uncorrelated sample of size 16,384 from the exact posterior distribution in under four hours. Less ambitious applications take as little as 4 minutes without exploiting GPUs.     

Design of Two-phase SABL Flip-flop for Resistant DPA Attacks

Differential power analysis （DPA） poses a great threat to cipher security circuit since it exploits the dependency between the processed data and the power consumption. Two-phase Sense amplifier based logic （Two- phase SABL） suitable to DPA resistant logic style has been introduced under unbalanced load conditions. The pro- posed logic obtains constant energy consumption per clock cycle with pre-charge and evaluation phases. In this paper, Two-phase SABL cell and flip-flop are designed and simu- lated to confirm the energy balancing characteristic. Using TSMC 0.13μm CMOS technique, simulation results show that the power consumption fluctuations in the flip-flop is decreased by 15.1% under unbalanced condition and the area is reduced by 38.4%.     

防DPA攻击的两种不同逻辑比较研究

DPA是一种非常有效的密码处理器攻击技术,它能够通过对密码处理器的功耗行为进行分析来获取密钥值。运用功耗恒定的标准单元实现密码处理器可以很好地达到防DPA攻击的目的。本文针对不同的集成电路制造工艺,分别对DIX2VSL与SABL两种不同逻辑的防DPA攻击特性进行比较分析。实验结果表明．随着晶体管沟道长度的减小,内部节点电容容对功耗恒定特性的作用逐渐减小,DDCVSL与SABL具有相近的防DPA攻击特性。同时,DDCVSL的功耗、延迟与面积小于SABL。     

采用混合MTJ/CMOS和SABL结构的密码算法电路设计

为了在提高轻量级密码算法(Lightweight cipher algorithm, LWCA)电路安全性的同时降低功耗,提出了一种磁隧道结(Magnetic tunnel junction, MTJ)/CMOS混合结构查找表(Look up table, LUT)电路,该结构通过与感测放大器逻辑(Sense amplifier based logic, SABL)元件配合可以实现完整的PRESENT-80加密算法电路。设计将MTJ器件引入防护电路设计中,进而提出了一种基于混合MTJ/CMOS结构的双轨查找表(Look-up table, LUT)电路结构。首先,基于40 nm CMOS工艺库和MTJ器件仿真模型,使用新提出的双轨查找表结构设计了加密算法电路工作过程中所需要的关键S-box电路并通过了仿真验证。然后,利用该电路和敏感放大器逻辑元件电路结构组合设计了PRESENT-80密码算法的完整电路。最后对所设计的电路模型进行了相关性功耗分析攻击(CPA)攻击,同时为了方便进行对比研究,还对使用传统CMOS单轨和SABL双轨结构实现的PRESENT-80加密算法电路模型进行了相同条件...     

防DPA攻击的标准单元库的设计与实现

给出了一个功耗恒定标准单元库的设计实现方法,并利用该标准单元库实现了DES密码算法中的S-盒。实验结果表明,这种标准单元库能够很好地起到防DPA攻击的作用。