一族Liouville可积系及其双约束流的Hamilton系统

构造了Loop代数 A2的一个子代数,由此建立了一个3×3等谱问题,由屠规彰格式得到了一族Liouville意义下的可积Hamilton方程族。通过建立双对称约束,得到了该方程族的两组约束流,并将其化为广义Hamilton系统。     

基于锁相同步检测的数字化阻抗测试方法

介绍了一种数字化阻抗测试方法，它采用锁相同步采样、数字化矢量电压电流比法及校准技术测试元器件或线路阻抗。同时介绍了相应实验电路原理，并结合线路接口，进行了通信电缆的线路阻抗测试实验。     

一种新颖的跳频振荡器

摘要本文综合考虑到频率合成技术及单端口体波谐振器HBAR的特点提出了一种基于一阶非线性PLL的锁相频率合成方案。文中对这种跳频方案的原理、性能特点作了详细论述、并通过实验、从不同角度对本方案进行了说明、同时对整机的各项指标作了详尽测试:在HBAR无载Q_N值为4000的情况下,该多模跳频振荡源的捷变范围为770MHz—840MHz、捷变时间小于20μS。杂散分量低于—60dB、二次谐波分量低于—34dB。离散捷变频率点为16点,构成闭环跳频系统后,对开环VCO的短稳改善了三个量级:从1.3×10~(-5)/ms到1.6×10~(-8)/ms及9.56×~(-7)/s到1.69×!0~(-9)/s,尤为重要的是该多模跳频振荡源达到此性能所需的硬件量很小,因此在对体积要求苛刻的场合、此种跳频方案具有极强的竞争力。     

A singular loop transformation framework based on non-singular matrices

In this paper, we discuss a loop transformation framework that is based on integer non-singular matrices. The transformations included in this framework are called Λ-transformations and include permutation, skewing and reversal, as well as a transformation calledloop scaling. This framework is more general than existing ones; however, it is also more difficult to generate code in our framework. This paper shows how integer lattice theory can be used to generate efficient code. An added advantage of our framework over existing ones is that there is a simple completion algorithm which, given a partial transformation matrix, produces a full transformation matrix that satisfies all dependences. This completion procedure has applications in parallelization and in the generation of code for NUMA machines. This work was supported by the Cornell Theory Center, NSF Presidential Young Investigator award #CCR-8958543. by NSF Grant #CCR-9008526, and by a grant from the Hewlett-Packard Company.     

Some efficient solutions to the affine scheduling problem. Part II. Multidimensional time

This paper extends the algorithms which were developed in Part I to cases in which there is no affine schedule, i.e. to problems whose parallel complexity is polynomial but not linear. The natural generalization is to multidimensional schedules with lexicographic ordering as temporal succession. Multidimensional affine schedules, are, in a sense, equivalent to polynomial schedules, and are much easier to handle automatically. Furthermore, there is a strong connection between multidimensional schedules and loop nests, which allows one to prove that a static control program always has a multidimensional schedule. Roughly, a larger dimension indicates less parallelism. In the algorithm which is presented here, this dimension is computed dynamically, and is just sufficient for scheduling the source program. The algorithm lends itself to a divide and conquer strategy. The paper gives some experimental evidence for the applicability, performances and limitations of the algorithm.     

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22 GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6 dBc/Hz at 1 MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1 mW. The chip with an area of 1.048 × 1.076 mm² is fabricated in a TSMC 0.18 μm CMOS 1P6M technology process.     

Feature-Adaptive Rendering of Loop Subdivision Surfaces on Modern GPUs

We present a novel approach for real-time rendering Loop subdivision surfaces on modern graphics hardware. Our algorithm evaluates both positions and normals accurately, thus providing the true Loop subdivision surface. The core idea is to recursively refine irregular patches using a GPU compute kernel. All generated regular patches are then directly evaluated and rendered using tile hardware tessellation unit. Our approach handles triangular control meshes of arbitrary topologies and incorporates common subdivision surface features such as semi-sharp creases and hierarchical edits. While surface rendering is accurate up to machine precision, we also enforce a consistent bitwise evaluation of positions and normals at patch boundaries. This is particularly useful in the context of displacement mapping which strictly requires inatching surface normals. Furthermore, we incorporate efficient level-of-detail rendering where subdivision depth and tessellation density can be adjusted on-the-fly. Overall, our algorithm provides high-quality results at real-time frame rates, thus being ideally suited to interactive rendering applications such as video games or authoring tools.     

内循环流化床固体循环速率的研究

研究一种加料不独立的垂直气力输送装置，并以流化床作为料仓和混合区，两者构成固体循环系统。由于系统特性，加料喷嘴的插入高度与加料结构将会直接影响操作的稳定性，从力的平衡出发导出临界结构为ｈｅ／Ｄｅ＜ｆＨＬ／Ｒ，其中ｆ是颗粒特性的函数。     

A novel clock generation algorithm for system-on-chip based on least common multiple

Due to increase in the number of Intellectual Property (IP) cores, clock generation in current day System-on-Chips (SoCs) is facing a crisis. The conventional method of using a dedicated Phase Locked Loop (PLL) to generate the clock for each IP core is becoming inefficient in terms of power and cost. We propose an algorithm based on Least Common Multiple (LCM) to minimize the number of PLLs required to generate the clocks for the IP cores in a SoC. This is done by finding an Optimum Operating Frequency (OOF) for each IP core within 10% below the maximum operating frequency of the core. The OOF is chosen such that the LCM of the OOF of all the IP cores is minimized. Simulated annealing is used to find the LCM. This LCM is the crucial high frequency from which maximum number of clocks can be derived by clock dividers.