Compiler technology for future microprocessors

Advances in hardware technology have made it possible for microprocessors to execute a large number of instructions concurrently (i.e., in parallel). These microprocessors take advantage of the opportunity to execute instructions in parallel to increase the execution speed of a program. As in other forms of parallel processing, the performance of these microprocessors can vary greatly depending on the qualify of the software. In particular the quality of compilers can make an order of magnitude difference in performance. This paper presents a new generation of compiler technology that has emerged to deliver the large amount of instruction-level-parallelism that is already required by some current state-of-the-art microprocessors and will be required by more future microprocessors. We introduce critical components of the technology which deal with difficult problems that are encountered when compiling programs for a high degree of instruction-level-parallelism. We present examples to illustrate the functional requirements of these components. To provide more insight into the challenges involved, we present in-depth case studies on predicated compilation and maintenance of dependence information, two of the components that are largely missing from most current commercial compilers     

Solar panel scattering effects on reflector antenna performance

The effects of solar panel scattering on a Ku-Band reflector antenna performance are analysed. It is shown from computation and experiment that the solar panel scattering interference causes mainlobe gain decrease and sidelobe gain increase on the sum patterns, as well as null position shift and null depth decrease on the difference patterns     

Interlaminar stresses around hole boundaries of composite laminates subjected to in-plane loading

Due to the complex stress state near the curvilinear edge of composite laminates, three-dimensional (3D) finite element analysis is usually applied even it is time consuming. In this paper, in order to save computer time and storage, an asymptotic analysis is employed to separate the 3D problem into two plane problems. One is an interior problem, the other is a boundary layer problem. The former is treated by classical lamination theory and is solved by a special boundary element, the latter is then solved by the finite element developed for the generalized plane deformation problems. When the ratio of laminate thickness to hole diameter is small, the solutions for the laminates containing a circular hole are in good agreement with those obtained by the 3D finite element method.     

Effect of citrate on poly(vinyl pyrrolidone)-stabilized gold nanoparticles formed by PVP reduction in microwave (MW) synthesis

Colloidal PVP (poly(vinyl pyrrolidone))–stabilized gold nanoparticles (PVP–AuNPs) are synthesized in aqueous solution with PVP as a reducing and stabilizing agent using a short microwave (MW) heating duration of 1 min. The size and uniformity of the synthesized PVP–AuNPs can be varied by modifying the concentration of sodium citrate (Na₃Ct), which acts predominantly as mediator of the stability of PVP–AuNP formation during the rapid synthesis. Due to the increase in the Na₃Ct concentration, the number of citrate ions adsorbed on the growing surface of AuNPs increase, and less reactive gold solute complexes are formed, leading to slow stable reactions that produce small, uniform colloidal PVP–AuNPs. We therefore demonstrate that by adjusting the Na₃Ct concentration used in the PVP reduction, the diameter of PVP–AuNPs was varied from 19.47 ± 3.97 nm to 7.94 ± 0.14 nm when using constant concentrations of chloroauric acid (HAuCl₄) and PVP.     

Geocomposite sheet drain joining

This short paper is focused on the joining of the edges and/or ends of geocomposite sheet drain panels or rolls to one another, or to their outlet structures. Experimental data are given for the amount of overlap needed for tensile strength mobilization and details are provided on various outlet connections.     

Incremental compiler transformations for multiple instruction retry

Previous work on compiler-based multiple instruction retry has utilized a series of compiler transformations, loop protection, node splitting, and loop expansion, to eliminate anti-dependencies of length ≤ N in the pseudo register, the machine register, and the post-pass resolver phases of compilation.¹ The results have provided a means of rapidly recovering from transient processor failures by rolling back N instructions. This paper presents techniques for improving compilation and run-time performance in compiler-based multiple instruction retry. Incremental updating enhances compilation time when new instructions are added to the program. Post-pass code rescheduling and spill register reassignment algorithms improve the run-time performance and decrease the code growth across the application programs studied. Branch hazards are shown to be resolvable by simple modifications to the incremental updating schemes during the pseudo register phase and to the spill register reassignment algorithm during the post-pass phase.