利用物理气相淀积工艺制备的HfTaON薄膜热力学稳定性研究

We investigate the thermal stability of HfTaON films prepared by physical vapor deposition using high resolution transmission electronic microscope （HRTEM） and X-ray photoelectron spectroscopy （XPS）. The results indicate that the magnetron-sputtered HfTaON films on Si substrate are not stable during the post-deposition annealing （PDA）. HfTaON will react with Si and form the interfacial layer at the interface between HfTaON and Si substrate. Hf-N bonds are not stale at high temperature and easily replaced by oxygen, resulting in significant loss of nitrogen from the bulk film. SiO2 buffer layer introduction at the interface of HfraON and Si substrate may effectively suppress their reaction and control the formation of thicker interfacial layer. But SiO2 is a low k gate dielectric and too thicker SiO2 buffer layer will increase the gate dielectric＇s equivalent oxide thickness. SiON prepared by oxidation of N-implanted Si substrate has thinner physical thickness than SiO2 and is helpful to reduce the gate dielectric＇s equivalent oxide thickness.     

金属栅回刻平坦化技术

随着CMOS集成电路技术节点缩减到45 nm及以下,高K金属栅(HK/MG)的后栅集成工艺已逐渐成为先进集成电路制造中的主流技术。其中金属栅(假栅)集成结构的平坦化是实现后栅集成的关键技术之一。本文通过特色开发的SOG两步等离子体回刻结合O2原位处理技术,克服了常规反应离子刻蚀中由于聚合物分布不均对刻蚀速度带来的不利影响,实现了隔离绝缘层低达4.19%(边缘去除5 mm)的片内非均匀性。不同稀疏与密集线阵列的亚微米CMOS后栅结构表明良好的平坦化效果并且避免了类似CMP(Chemical Mechanical Polish)工艺中常出现的"碟形效应"问题。所研制成功的无CMP后栅平坦化工艺为制备纳米级高K金属栅CMOS后栅器件打下了重要基础。     

先栅工艺中高K/双金属栅集成研究新进展

随着高K、金属栅材料引入到CMOS工艺,高K/双金属栅的集成已成为研究热点.利用多晶硅回刻和摻杂结合两步全硅化工艺的方案,可实现低功耗和高性能电路的高K与双FUSI金属栅的集成.采用淀积-刻蚀-再淀积、双高K双金属栅的集成方案,也可实现高K与双金属栅的集成.为缓解费米能级钉扎效应,通过盖帽层或离子注入技术对高K或金属栅掺杂,可得到具有带边功函数的高K/双金属栅集成.多晶硅/金属栅复合结构为高K与双金属栅的集成提供了更灵活的选择.     

Selective wet etch of a TaN metal gate with an amorphous-silicon hard mask

The appropriate wet etch process for the selective removal of TaN on the HfSiON dielectric with an amorphous-silicon(a-Si) hardmask is presented.SCI(NH_4OH:H_2O_2:H_2O),which can achieve reasonable etch rates for metal gates and very high selectivity to high-k dielectrics and hardmask materials,is chosen as the TaN etchant. Compared with the photoresist mask and the tetraethyl orthosilicate(TEOS) hardmask,the a-Si hardmask is a better choice to achieve selective removal of TaN on the HfSiON dielectric be...     

电子束光刻在纳米加工及器件制备中的应用

电子束光刻技术是推动微米电子学和微纳米加工发展的关键技术,尤其在纳米制造领域中起着不可替代的作用。介绍了中国科学院微电子研究所拥有JEOLJBX5000LS、JBX6300FS纳米电子束光刻系统和电子显微镜系统的电子束光刻技术实验室,利用电子束直写系统所开展的纳米器件和纳米结构制造工艺技术方面的研究。重点阐述了如何利用电子束直写技术实现纳米器件和纳米结构的电子束光刻。针对电子束光刻效率低和电子束光刻邻近效应等问题所采取的措施;采用无宽度线曝光技术和高分辨率、高反差、低灵敏度电子抗蚀剂相结合实现电子束纳米尺度光刻以及采用电子束光刻与X射线曝光相结合的技术实现高高宽比的纳米尺度结构的加工等具体工艺技术问题展开讨论。     

面向积极生活的建成环境量表比较研究

Nowadays, chronic non-communicable diseases have impacted the overall public health level of societies and caused severe socio-economic burden. Empirical studies have revealed that physical activities can promote active living and help prevent and heal non-communicable diseases. Evaluation of built environment factors associated with physical activities is the precondition of promoting active living through environmental planning and design. This paper focuses on environmental audit tools related to physical activities, reviews the background, interests, and progress of international research, and compares the option forms, main measured factors, scoring methods, and application suitability of 26 audit tools. It then categorizes these audit tools into the ones for community, open space, and other scenarios, and examines their indicator items respectively. The paper concludes a preparation pattern across various audit tools, and identifies that facilities, accessibility, visual quality, and safety are the indicators most commonly measured. This paper attempts to introduce international experience of developing, analyzing, and verifying audit tools to inform Chinese research and practice and provide references for evaluating the design and construction of healthy cities or communities.     

部分耗尽0.25μm SOI射频nMOSFET

结合多项用于深亚微米集成电路的新技术,提出了用于数GHz射频集成电路的SOI nMOSFET器件结构和制造工艺.经过半导体工艺模拟软件Tsuprem4仿真和优化,给出了主要的工艺步骤和详细的工艺条件.制作了0.25μm SOI射频nMOSFET器件,结构和工艺参数同仿真结果一致,测试获得了优良的或可接受的直流及射频性能.     

SAL601负性电子束抗蚀剂纳米级集成电路加工

讨论了采用SAL6 0 1负性化学放大电子束抗蚀剂进行电子束曝光应用于纳米级集成电路加工的实验方法与工艺条件。经过大量实验总结 ,通过变剂量模型对电子束曝光中电子散射参数进行提取 ,应用于邻近效应校正软件 ,针对集成电路曝光图形进行邻近效应校正。校正后的曝光图形经过曝光实验确定显影时间及曝光剂量 ,最终得到重复性良好的 ,栅条线宽为 70nm的集成电路曝光图形     

部分耗尽0.25μmSOI射频nMOSFET

结合多项用于深亚微米集成电路的新技术,提出了用于数GHz射频集成电路的SOI n MOSFET器件结构和制造工艺.经过半导体工艺模拟软件Tsuprem4仿真和优化,给出了主要的工艺步骤和详细的工艺条件.制作了0 .2 5 μm SOI射频n MOSFET器件,结构和工艺参数同仿真结果一致,测试获得了优良的或可接受的直流及射频性能     

恒压应力下超薄Si_3N_4/SiO_2叠层栅介质与SiO_2栅介质寿命比较

以等效氧化层厚度(EOT)同为2.1nm的纯SiO2栅介质和Si3N4/SiO2叠层栅介质为例,给出了恒定电压应力下超薄栅介质寿命预测的一般方法,并在此基础上比较了纯SiO2栅介质和Si3N4/SiO2叠层栅介质在恒压应力下的寿命.结果表明,Si3N4/SiO2叠层栅介质比同样EOT的纯SiO2栅介质有更长的寿命,这说明Si3N4/SiO2叠层栅介质有更高的可靠性.