长空气间隙电弧的阻抗特性(英文)

Arc resistance is an important parameter for characterizing long arcs in air, and its laboratory testing is of importance for accurate arc modeling of electromagnetic transient caused by short circuit fault. Therefore, we constructed an experimental system to study the cha- racteristics of long AC arc in air. Driven by currents of 10 kA or 40 kA (root mean square value), the system produces arcs with different initial lengths of 1 m, 2 m and 4 m, and the movement of the arcs are captured by a high-speed camera. After performing experiments using the system, we carried out analysis and comparisons of the arc resistance of arcs with different lengths and different currents, as well as a study of the relationship between the macro-morphology and the resistance of the arcs. Conclusions were drawn from the experimental re- sults: the arc voltage had obvious saturation characteristics; the arc resistance increased with the increase of arc length and the decrease of current; the arcs bended or extended significantly in time and the peak arc voltage within a single cycle increased correspondingly; the arcs had voltage and current in the same phase. In the end, a formula of arc resistance based on the experiment results is derived.     

小面积低功耗掩膜ROMASIC设计

本文介绍了一种利用0.6μm单硅双铝双阱CMOS工艺实现的4Kbit掩膜ROM专用集成电路设计(ASIC).ROM单元应用串行结构,整个芯片的面积为0.082mm².在5伏电源下,功率延迟积为0.036PJ/bit,最大工作电流为1.2mA,最大静态漏电流为0.1μA.采用一种新颖的灵敏放大器有效地提高了ROM的访问速度,ROM的访问时间为36ns.     

配电网络断线谐振及抑制方法

通过模拟试验，从典型的断线回路中揭示出断线谐振的许多性质及其产生规律，提出了瞬间吸能配以附加相间电容的消谐方法，研制的消谐装置能够满足现场的实际需要。     

基于FPGA的时变带宽数字滤波器的研究和设计

介绍了一种采用切比雪夫逼近算法估计滤波器的系统传输函数、按照频率乘积法基于FPGA实现窄带FIR数字滤波器的方法。通过分析设计指标中对纹波和阻带衰减的要求,确定了以切比雪夫逼近算法作为理论基础,采用MATLAB数学工具实现该算法;采用VHDL硬件描述语言描述了频率乘积法的RTL级实现结构,并通过了硬件电路测试满足了设计的要求。通过本论文论证了切比雪夫逼近法在FIR滤波器基于FPGA设计可行性。     

并联电抗器中性点小电抗的选择

分析并列出了四射线补偿方法下并联电抗器在不同的补偿度下小电抗的大小、所应耐受的最大工频电压和暂时功率的计算公式 ,并给出了相应的曲线。指出应该避开电抗器的全补偿运行方式。超高压线路中的可控电抗器应具有高速响应能力 ,文中叙述了它的三角形接线的优点 ,以及星形接线时的调节方式     

ASIC Design of High-Speed Low-Power HDLC Controller

Combined with the engineering requirement, a high-speed low-power ASIC design of HDLC controllerbased on RS-485 bus is given in this paper.On principle of Top-Down design, this ASIC design usesmulti-techniques to reduce its die area and dynamic power,and overcomes some problems appeared frequently inapplication systems of the RS-485 circuits formed by the Standard Interface Chips. This design also improves thesystem reliability and reduces the system area.     

uC/OS-Ⅱ支持下的以太网数据采集系统的设计

针对在嵌入式系统中采用“线性”程序设计方法带来的实时性差和扩展性不高的问题,通过在一个嵌入式数据采集系统中移植嵌入式实时操作系统uC/OS-Ⅱ,在分析了在实时操作系统uC/OS-Ⅱ下,确定了系统各个任务的优先级并实现了任务间的相互切换,提高了系统运行实时性和稳定性;数据采集系统移植了传输效率更高的UDP/IP协议栈,实现了系统的网络通信功能;实验表明,数据采集系统在移植了uC/OS-Ⅱ具有良好的实时性和扩展性并且运行稳定.     

基于FFT的两种伪码快速捕获方案的研究与实现

该文提出两种基于FFT的伪码快速捕获方案,一种是基于分数倍采样率转换器的快捕方案;另一种是基于抽取器的快捕方案。两种伪码快捕电路均利用设计复用技术使硬件规模大幅减少;采用并行设计使系统的运算速度大大提高;采用块浮点算法以提高动态范围和运算精度。两种快捕电路均由一块FPGA实现。仿真和测试结果表明,基于分数倍采样率转换器的快捕电路与基于抽取器的快捕电路相比,占用的硬件资源较大,但是捕获精度更高。     

DSP与PC机之间异步串行接口设计

阐述了DSP通过RS-232-C与PC机的异步串行通信原理,并给出了实现异步串行通信的硬件接口电路设计实例和软件编程.该方案简单易行,具有一定的通用性.     

±800 kV换流变压器阀侧交流耐压试验局部放电超标分析

在云广直流输电工程HY12换流变压器阀侧绕组交流外施耐压带局部放电测量试验中,发现其2.1套管放电超标。基于阀侧绕组在绝缘试验过程中的场域分布和试验加压过程数据,分析了局部放电回路,结论为：局部放电超标是由于2.1套管内部局部放电造成。采取更换2.1套管的措施后,成功地通过了试验。