Research on COB De-embedding in Scattering Parameter Measurement

The popular radio frequency (RF) chip on board (COB) test has gradually taken the place of on-wafer test due to the high efficiency and high power. This paper presents the extended Open-Short-Load (OSL) that is one-port calibration method to verify the error model de-embedding in S parameter measurement. Three-level cascade structure on COBs system error model is proposed and analyzed. Four kinds of calibration plane solutions for de-embedding are verified. At last, on-board calibration (CAL) kits solution is established to decrease the system error to the least value. The maximum error shift can be controlled less than 0.1 dB comparing with the on-wafer test results. In general, the practical application results prove that this method is reasonable and effective and easy to be mastered.     

钨化学气相淀积工艺方块电阻均匀性的研究

钨化学气相淀积因为其在接触孔/通孔填充中出色的台阶覆盖能力而在半导体工业中被广泛应用,在量产中经常会出现监控片的方块电阻均匀性超规格。本文主要研究了加热器、气体输送、氟化铝、机械传片定位、真空微漏等因素对方块电阻均匀性的影响,特别周期性等离子清洗产生的氟化铝对晶圆边缘的抑制反应是影响腔体维护频率的主要原因,并提出改善均匀性的有效办法。     

A novel sourceline voltage compensation circuit for embedded NOR flash memory

A novel sourceline voltage compensation circuit for program operation in embedded flash memory is presented. With the sourceline voltage compensation circuit, the charge pump can modulate the output voltage according to the number of cells to be programmed with data ＂0＂. So the IR drop on the sourceline decoding path is compensated, and a stable sourceline voltage can be obtained. In order to reduce the power dissipation in program operation, a bit-inversion program circuit is adopted. By using the bit-inversion program circuit, the cells programmed to data ＂0＂ are limited to half of the bits of a write data word, thus power dissipation in program operation is greatly reduced. A 1.8-V 8 × 64-kbits embedded NOR flash memory employing the two circuits has been integrated using a GSMC 0.18-μm 4-poly 4-metal CMOS process.     

An effective approach to improve split-gate flash product data retention

Data retention is one of the most important reliability characteristics of split-gate flash. Therefore, many efforts were made to improve data retention of split-gate flash. By experiments, it was found that higher chlorine concentration produced in FGSP2 oxide deposition can induce worse data retention. Thus, reducing chlorine concentration is an effective approach to improve data retention for split-gate flash product. Additional RTO annealing between FGSP2 oxide deposition and FGSP2 etching could reduce chlorine concentration, and improve FGSP2 oxide film quality, and then get better data retention.     

Program efficiency and high temperature retention of SiN/high-K based memories

This paper presents an experimental and simulation study of the program efficiency and retention of SANOS memory cells. We analyzed the experimental curves of the available cells by a physics based model that includes drift-diffusion transport of carriers in the nitride conduction band. We evidenced how the gate stack dimensions impact the program efficiency; in particular, thicker Si₃N₄ layers allow for faster programming. However, the Si₃N₄ thickness hardly influence the high temperature retention, since charge loss due to thermal emission dominates. Good agreement of the model with a wide set of experiments makes us confident on the validity of the interpretation of data which is suggested by the modeling results.     

A broadband Low Noise Amplifier with built-in linearizer in 0.13-µm CMOS process

A linearized ultra-wideband (UWB) CMOS Low Noise Amplifier (LNA) is presented in this paper. The linearity performance is enhanced by exploiting PMOS–NMOS common-gate (CG) inverter as a built-in linearizer which leads to cancel out both the second- and third-order distortions. Two inductors are placed at the drain terminals of CG transistors in the built-in linearizer to adjust the phase and magnitude of the third-order distortion. A second-order band-pass Chebyshev filter is utilized in the input port of common-source (CS) configuration to provide broadband input matching at 3.1–10.6 GHz frequency range to a 50-Ω antenna. Series and shunt peaking techniques are employed to extend the bandwidth (BW) and to flatten the gain response. Simulated in 0.13 µm CMOS technology, the CMOS LNA exhibits state of the art performance consuming 17.92 mW of dc power. The CMOS LNA features a maximum gain of 10.24 dB, 0.9–4.1 dB noise figure (NF), and a third-order input intercept point (IIP3) of 6.8 dBm at 6.3 GHz.     

Noise canceling LNA with gain enhancement by using double feedback

In this paper we present a balun low noise amplifier (LNA) in which the gain is boosted by using a double feedback structure. The circuit is based on a conventional balun LNA with noise and distortion cancelation. The LNA is based on the combination of a common-gate (CG) stage and common-source (CS) stage. We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with a 130 nm CMOS technology, show that the gain is 24 dB and the NF is less than 2.7 dB. The total power dissipation is only 5.4 mW (since no extra blocks are required), leading to a figure-of-merit (FOM) of 3.8 mW⁻¹ using a nominal 1.2 V supply. Measurement results are presented for the proposed DFB LNA included in a receiver front-end for biomedical applications (ISM and WMTS).     

A 10-bit 2.5-MS/s SAR ADC with 60.46 dB SNDR in 0.13-μm CMOS technology

This paper presents a 10-bit 2.5-MS/s successive-approximation-register (SAR) analog- to-digital-converter (ADC) design for micro controller unit of signal process system. Because of the proposed new segmented architecture of 7 MSBs-plus-3 LSBs capacitor–resistor hybrid digital-to-analog-converter using a thermometer decoder for the most significant 5 MSBs, this design achieves superior static nonlinearity and dynamic performance of SNDR, SFDR. Utilizing the proposed deviation calibration technique, the discharging and charging via substrate resulting from deviation of the comparator’s common-mode voltage is cancelled. The ADC is fabricated in a standard 1P5M 0.13-μm CMOS technology. The peak DNL and INL are +0.18/?0.20-LSB, +0.30/?0.25 LSB respectively while the ENOB is 9.52-bit around all process–voltage–temperature corner analysis. At a 2.3-V supply voltage and a 2.5-MS/s sampling rate, the ADC achieves a SNDR of 60.46 dB, SFDR of 75.32 dB while the power dissipation is 0.191-mW, that resulting in a figure of merit of 98.45 fJ/c-s. The die of ADC measures 0.51 × 0.20 mm² resulting in area efficiency of 122.6 μm²/code and compared with the benchmark SAR ADCs, this work is the most area efficient design.     

A resistive-feedback LNA in 65 nm CMOS with a gate inductor for bandwidth extension

In order to get a wideband and flat gain, a resistive-feedback LNA using a gate inductor to extend bandwidth is proposed in this paper. This LNA is based on an improved resistive-feedback topology with a source follower feedback to match input. A relative small inductor is connected in series to transistor׳s gate, which boosts transistor׳s effective transconductance, compensates gain loss and then leads the proposed LNA with a flat gain and wider bandwidth. Moreover, the LNA׳s noise is partially inhibited by the gate inductor, especially at high frequency. Realized in standard 65-nm CMOS process, this LNA dissipates 12 mW from a 1.5-V supply while its core area is 0.076 mm². Across 0.4–10.6 GHz band, the proposed LNA provides 9.5±0.9 dB power gain (S₂₁), better than −11-dB input matching, 3.5-dB minimum noise figure, and higher than −17.2-dBm P_1 dB.