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21.
A self-assembly patterning method for generation of epitaxial CoSi2 nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n+-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO2 and 300 nm Si3N4. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi2 layer and a subsequent out-diffusion process to form the n+-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated. 相似文献
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A simple template‐free high‐temperature evaporation method was developed for the growth of crystalline Si microtubes for the first time. As‐grown Si microtubes were characterized using X‐ray diffraction, scanning electron microscopy, transmission electron microscopy, and room‐temperature photoluminescence. The lengths of the Si tubes can reach several hundreds of micrometers; some of them have lengths on the order of millimeters. Each tube has a uniform outer diameter along its entire length, and the typical outer diameter is ≈ 2–3 μm. Most of the tubes have a wall thickness of ≈ 400–500 nm, though a considerable number of them exhibit a very thin wall thickness of ≈ 50 nm. Room‐temperature photoluminescence measurement shows the as‐synthesized Si microtubes have two strong emission peaks centered at ≈ 589 nm and ≈ 617 nm and a weak emission peak centered at ≈ 455 nm. A possible mechanism for the formation of these Si tubes is proposed. We believe that the present discovery of the crystalline Si microtubes will promote further experimental studies on their physical properties and smart applications. 相似文献
25.
P. G. Muzykov Y. I. Khlebnikov S. V. Regula Y. Gao T. S. Sudarshan 《Journal of Electronic Materials》2003,32(6):505-510
To establish fast, nondestructive, and inexpensive methods for resistivity measurements of SiC wafers, different resistivity-measurement
techniques were tested for characterization of semi-insulating SiC wafers, namely, the four-point probe method with removable
graphite contacts, the van der Pauw method with annealed metal and diffused contacts, the current-voltage (I-V) technique,
and the contactless resistivity-measurement method. Comparison of different techniques is presented. The resistivity values
of the semi-insulating SiC wafer measured using different techniques agree fairly well. As a result, application of removable
graphite contacts is proposed for fast and nondestructive resistivity measurement of SiC wafers using the four-point probe
method. High-temperature van der Pauw and room-temperature Hall characterization for the tested semi-insulating SiC wafer
was also obtained and reported in this work. 相似文献
26.
研究了深亚微米PD和FD SOI MOS器件遭受热截流子效应(HCE)后引起的器件参数退化的主要差异及其特点,提出了相应的物理机制,以解释这种特性。测量了在不同应力条件下最大线性区跨导退化和闽值电压漂移,研究了应力Vg对HCE退化的影响,并分别预测了这两种器件的寿命,提出了10年寿命的0.3μm沟长的PD和FD SOI MOS器件所能承受的最大漏偏压。 相似文献
27.
Ultra thin (5 nm) silicon oxynitride (SiON) films were fabricated at a low temperature using nitrogen plasma generated by an inductively coupled plasma system. Effects of post-metalization annealing (PMA) of Al/SiON/Si MOS structure on the electrical properties of the SiON films were studied and correlations between the charge trapping states and the leakage current were established. Positive charge trapping by interface states generated by plasma damage was characterized by the hysteresis in high-frequency capacitance-voltage (C-V) characteristics. Hysteresis was observed to be completely removed by PMA while interface state density at the Si mid band gap reduced from 2.2×1013 to 3.7×1011/eV/cm2 and the oxide fixed charge density changed from 3.3×1012 to −4×1011/cm2. The leakage current also decreased significantly, by more than two orders of magnitude, with PMA. The analysis of the leakage current using trap assisted tunneling (TAT) mechanism indicated that with PMA, the trap energy level in the SiON film becomes shallower from 1.3 to 0.7 eV. The positive trapped charges were observed to be annihilated by PMA and the trapping sites became neutral trap centers in the SiON film. This could lead to the reduction in the leakage current component given rise to by TAT. 相似文献
28.
A critical review of the current status of tungsten resources, of state-of-the-art processing technology and of product development
in India vis-a-vis the world scenario is presented. An attempt has been made to identify technology gap areas requiring attention. 相似文献
29.
LDD方法在提高电路工作电压中的应用研究 总被引:1,自引:0,他引:1
研究了利用轻掺杂漏结构来制作高电源电压器件的工艺方法。分析了LDD结构参数对器件击穿特性的影响,并结合实验结果对N^-区的注入剂量,长度及引入的串联电阻进行了优化设计。 相似文献
30.
NMOS器件两次沟道注入杂质分布和阈电压计算 总被引:1,自引:1,他引:0
分别考虑了深浅两次沟道区注入杂质在氧化扩散过程中对表面浓度的贡献。对两次注入杂质的扩散分别提取了扩散系数的氧化增强系数、氧化衰减系数和有效杂地系数,给出了表面浓度与工艺参数之间的模拟关系式,以峰值浓度为强反型条件计算了开启电压,文章还给出了开启电压、氧化条件、不同注入组合之间的关系式。 相似文献