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81.
82.
射频直采技术近年来在雷达、通信、电子对抗尤其是一体化接收等领域得到了广泛的应用。然而射频采样数据率极高,导致后续信号传输与实时处理难度变大。数字重采样技术能够在数字域降低采样率,从而减轻射频直采带来的信号处理压力。本文针对数字重采样技术开展研究,提出一种整数抽取结合小数插值重采样方法,推导了理论模型,给出了相应的参数递推解算方法,仿真验证了方法的有效性。采用本文所提方法,既可解决在射频高采样率下,直接进行小数插值带来的数字信号实时处理压力,又可在保证信号质量的情况下,解决特殊场景下精确变采样率处理的需求,进而实现对大范围任意分数倍抽取。 相似文献
83.
Increasing chip densities and transistor counts provide more room for designers to add functionality for important application
domains into future microprocessors. As a result of rapid growth in financial, commercial, and Internet-based applications,
hardware support for decimal floating-point arithmetic is now being considered by various computer manufacturers and specifications
for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic
(IEEE P754). In this paper, we presents an efficient arithmetic algorithm and hardware design for decimal floating-point division.
The design uses an efficient piecewise linear approximation, a modified Newton–Raphson iteration, a specialized rounding technique,
and a simplified decimal incrementer and decrementer. Synthesis results show that a 64-bit (16-digit) implementation of the
decimal divider, which is compliant with the current version of IEEE P754, has an estimated critical path delay of 0.69 ns
(around 13 FO4 inverter delays) when implemented using LSI Logic’s 0.11 micron Gflx-P standard cell library.
相似文献
Michael J. SchulteEmail: |
84.
二路随机脉冲尾数求差法及其应用 总被引:1,自引:0,他引:1
介绍了一种对二路随机脉冲尾数术差的原理,并在此基础上提出用十进制求差的计算方法。同时,利用此方法成功地设计了一个可以级联的二路脉冲信号求BCD码差值的集成电路。该方法可用于精密数字测量系统的硬件设计。 相似文献
85.
一种改进编码机制在移动机器人路径规划中的应用 总被引:1,自引:0,他引:1
针对基于遗传算法的移动机器人路径规划,提出了一种新颖的可变长度十进制路径编码机制,并给出了相应此编码机制的遗传操作算子。仿真结果表明,所提算法简单有效。 相似文献
86.
文章讨论了在MCU中以BCD码为基础的十进制加减法运算,同时给出了设计代码,并使用自动测试方法对设计结果进行了完备集的测试,从而确保了设计的正确性。 相似文献
87.
88.
分析了遗传算法的二进制、实数、十进制编码策略实现方法,根据各编码的特点,设计了相应的改进遗传策略。以前馈神经网络权值优化问题为例,用计算机仿真实验的方法研究了三种编码策略对各遗传算法性能的影响。研究结果表明,若同时强调搜索效率和搜索准确性,宜采用实数编码的改进遗传算法;若只强调搜索准确性,则应优先考虑十进制编码的改进遗传算法。研究的结论为遗传算法在高维连续参数优化问题中编码策略的选取提供了理论指导。 相似文献
89.
Tatiana Koutchma Brian Parisi S. Kucuk Unluturk 《Chemical Engineering Communications》2006,193(6):715-728
High absorptivity and turbidity interfere with the UV disinfection of apple cider. Three different configurations of flow-through UV reactors were evaluated to overcome this interference. Two approaches were employed: use of an extremely thin film UV reactor and increasing the turbulence within a UV reactor. Multiple-lamp UV reactors including the thin-film laminar flow “CiderSure” (8 lamps) and turbulent flow “Aquionics” (12 lamps) and annular single-lamp “UltraDynamics” reactor were studied. UV disinfection performance in laminar and turbulent flow reactors was compared by evaluation of UV dose delivery. UV fluence rate (irradiance) distribution was calculated using the multiple point source summation method. E. coli K12 was used as a target bacterium in a bioassay, and the log reduction per one pass was determined for each UV reactor. Finally, the UV decimal reduction dose (D10) was calculated by dividing the average UV fluence by log bacterial reduction per pass. Variations of the UV decimal dose were observed with various designs of UV systems. The least inactivation of E. coli K12 but the highest UV decimal reduction dose, ranging from 90 to 150 mJ/cm2, was observed in the Aquionics UV reactor in apple cider with apparent absorption coefficient (a) of 5.7 mm-1. The lower value of UV decimal reduction dose of 7.3-7.8 mJ/cm2 was required for inactivation of E. coli K12 in malate buffer and apple juice in the annular single-lamp UltraDynamics reactor. However, the decimal reduction dose for E. coli K12 in apple cider was significantly higher, about 20.4 mJ/cm2. Similar UV decimal reduction doses from 25.1 to 18.8 mJ/cm2 for inactivation of E. coli K12 were observed in the thin-film 'CiderSure' UV reactor in apple cider with identical absorption coefficient. Mathematical modeling of UV irradiance can improve the evaluation of UV dose delivery and distribution within the reactors. 相似文献
90.
用单片机与FPGA实现的DDS波形发生器 总被引:1,自引:0,他引:1
本文提出了一种用单片机和FPGA实现DDS信号源的实现方案。通过采用十进制累加器消除了二进制频率控制原理存在的固有误差,提高了信号源精度。通过对波形数据的量化减少了所需的存储容量。文中详细介绍了十进制频率控制原理,并例举了一种100Hz~200KHz,步进100Hz的DDS波形发生器的参数设计及实现。仿真结果表明,该设计简单合理,能够有效的消除二进制频率控制原理存在的误差,整个系统在保证频率精度的同时可快速获得输出波形。 相似文献