Known Good Die

Advances in reducing size and increasing functionality of electronics have been due primarily to the shrinking geometries and increasing performance of integrated circuit technologies. Recently, development efforts aimed at reducing size and increasingfunctionality have focused on the first level of the electronicpackage. The result has been the development of multichip packaging,technologies in which bare IC chips are mounted on a single high density substrate that serves to package thechips, as well as interconnect them. A number of benefits accruebecause of multichip packaging, namely, increased chip density,space savings, higher performance, and less weight. Therefore, thesetechnologies are attractive for today's light weight, portable, highperformance electronic equipment and devices.In spite of these benefits, multichip packaging has not shown the kind of explosive growth and expansion that was predicted[1]. A major inhibitor for these technologies has been theavailability of fully tested and conditioned bare die, orknown good die. This paper reviews the issues and technologies associated with test and burn-in of bareor minimally packaged IC products.     

Fundamentals of MCM Testing and Design-for-Testability

Products motivated by performance-driven and/or density-driven goals often use Multi-Chip Module (MCM) technology, even though it still faces several challenging problems that need to be resolvedbefore it becomes a widely adopted technology. Among its mostchallenging problems is achieving acceptable MCM assembly yieldswhile meeting quality requirements. This problem can be significantlyreduced by adopting adequate MCM test strategies: to guarantee thequality of incoming bare (unpackaged) dies prior to module assembly;to ensure the structural integrity and performance of assembled modules; and to help isolate the defective parts and apply the repair process.This paper describes todays MCM test problems and presents thecorresponding test and design-for-testability (DFT) strategies usedfor bare dies, substrates, and assembled MCMs.     

A novel Ni2Mo3N/MCM41 catalyst for the hydrogenation of aromatics

Bulk and MCM41-supported Ni₂Mo₃N catalysts were prepared using a temperature-programmed reduction (TPR) method and characterized using XRD, TEM, ICP-AES, and N₂ adsorption analysis techniques. Their catalytic properties were measured for the simultaneous hydrogenation of p-xylene and naphthalene and compared with Ni/MCM41 and Mo₂N/MCM41 catalysts having similar metal loadings. The results indicate that the Ni₂Mo₃N/MCM41 catalyst exhibits excellent deep hydrogenation activity under mild condition (T = 483 K, P = 3.0 MPa), and that it is more active than either Ni/MCM41 or Mo₂N/MCM41 catalyst.     

基于LTCC基板微波互连技术的探究

基于低温共烧陶瓷(LTCC)技术已经成为无源元件集成的主流技术,对低温共烧陶瓷(LTCC)包括LTCC的工艺、基板上电路互连和基板上电路的布局等技术进行了深入的研究,在基板电路互连中我们得出接地通孔用梅花形排列更佳,传输线连接利用同心圆过孔连接更佳。该技术将加速国内电子装备的国产化进程,并产生良好的经济效益和社会效益。     

对抗艺术:让人离开雷区

随着水雷技术的进步,各国海军正在对其传统的反水雷舰艇进行现代化改装,研制无人水面和水下航行器,开发模块化使命组件,以使反水雷作战更安全和快速。     

MCM芯片互连技术

介绍了目前最为先进的 MCM(Multi-Chip Module多芯片模块 )技术 ,通过与传统封装技术的对比 ,介绍了 MCM技术的特点。重点讨论了 MCM技术最为关键的芯片互连技术     

MCM—41中孔分子筛的结构和性能研究

用Ｘ射线衍射仪,红外谱仪,固体魔角旋转核磁仪,电子自旋共振仪等表征手段,考察了ＭＣＭ－４１中孔分子筛的结构和性能,结果表明,ＭＣＭ－４１分子筛的结构不同于一般微孔分子筛和无定形硅胶,其孔墙结构类似于无定形硅酸盐的局域原子排布,反映在ＸＲＤ和＾２９ＳｉＭＡＳＮＭＲ谱上,孔壁分布均匀有序,但整体结构缺乏规整的长程序一维空间原子排布。酸性表明,ＭＣＭ－４１中孔分子筛酸中等,较Ｙ分子筛弱,在酯化,烷基化等     

LTCC微波多芯片组件中键合互连的微波特性

键合互连是实现微波多芯片组件电气互连的关键技术,键合互连的拱高、跨距和金丝根数对其微波特性具有很大的影响。本文采用商用三维电磁场软件HFSS和微波电路设计软件ADS对低温共烧陶瓷微波多芯片组件中键合互连的微波特性进行建模分析和仿真优化。仿真优化结果与LTCC试验样品的测试结果吻合较好。