Software Distributed Shared Memory: a VIA‐based implementation and comparison of sequential consistency with home‐based lazy release consistency

A Distributed Shared Memory (DSM) system provides a distributed application with a shared virtual address space. This article proposes a design for implementing the DSM communication layer on top of the Virtual Interface Architecture (VIA), an industry standard for user‐level networking protocols on high‐speed clusters. User‐level communication protocols operate in user mode, thus removing the operating system kernel's overhead from the critical communication pass, and significantly diminishing communication overhead as a result. We analyze VIA's facilities and limitations in order to ascertain which implementation trade‐offs can be best applied to our development of an efficient communication substrate optimized for DSM requirements. We then implement a multithreaded version of the Home‐based Lazy Release Consistency (HLRC) protocol on top of this substrate. In addition, we compare the performance of this HLRC protocol with that of the Sequential Consistency (SC) protocol in which a Multi View (MV) memory mapping technique was used. This technique enables a fine‐grained access to shared memory, while still relying on the virtual memory hardware to track memory accesses. We perform an ‘apple‐to‐apple’ comparison on the same testbed environment and benchmark suite, and investigate the effectiveness and scalability of both protocols. Copyright © 2005 John Wiley & Sons, Ltd.     

Fano Decoding with Timeout: Queuing Analysis

In mobile communications, a class of variable‐complexity algorithms for convolutional decoding known as sequential decoding algorithms is of interest since they have a computational time that could vary with changing channel conditions. The Fano algorithm is one well‐known version of a sequential decoding algorithm. Since the decoding time of a Fano decoder follows the Pareto distribution, which is a heavy‐tailed distribution parameterized by the channel signal‐to‐noise ratio (SNR), buffers are required to absorb the variable decoding delays of Fano decoders. Furthermore, since the decoding time drawn by a certain Pareto distribution can become unbounded, a maximum limit is often employed by a practical decoder to limit the worst‐case decoding time. In this paper, we investigate the relations between buffer occupancy, decoding time, and channel conditions in a system where the Fano decoder is not allowed to run with unbounded decoding time. A timeout limit is thus imposed so that the decoding will be terminated if the decoding time reaches the limit. We use discrete‐time semi‐Markov models to describe such a Fano decoding system with timeout limits. Our queuing analysis provides expressions characterizing the average buffer occupancy as a function of channel conditions and timeout limits. Both numerical and simulation results are provided to validate the analytical results.     

无线信元反向复用及动态容量调整技术研究

根据ATM无线链路组网需求,提出了适合无线链路反向复用的编码及动态容量调整技术。该技术适用于利用微波、散射和卫星等传输手段进行ATM/MPLS无线机动组网,编码纠错门限为2×10-3,当通信节点无线传输距离增大或信道传输质量变恶劣时,通过动态容量调整技术自动降低信号速率以提高业务传输质量,该项技术特别适合新一代宽带网络。     

半导体集成电路标准概述

半导体集成电路是半导体器件两大产业之一，对电子电气产业发展有着重要影响。主要介绍了半导体集成电路的产业现状。国内外相关标准概况以及标准发展动向等。     

Improving phrase-based statistical machine translation with morphosyntactic transformation

We present a phrase-based statistical machine translation approach which uses linguistic analysis in the preprocessing phase. The linguistic analysis includes morphological transformation and syntactic transformation. Since the word-order problem is solved using syntactic transformation, there is no reordering in the decoding phase. For morphological transformation, we use hand-crafted transformational rules. For syntactic transformation, we propose a transformational model based on a probabilistic context-free grammar. This model is trained using a bilingual corpus and a broad-coverage parser of the source language. This approach is applicable to language pairs in which the target language is poor in resources. We considered translation from English to Vietnamese and from English to French. Our experiments showed significant BLEU-score improvements in comparison with Pharaoh, a state-of-the-art phrase-based SMT system.     

Cache modeling and optimization for portable devices running MPEG-4 video decoder

There are increasing demands on portable communication devices to run multimedia applications. ISO (an International Organization for Standardization) standard MPEG-4 is an important and demanding multimedia application. To satisfy the growing consumer demands, more functions are added to support MPEG-4 video applications. With improved CPU speed, memory sub-system deficiency is the major barrier to improving the system performance. Studies show that there is sufficient reuse of values for caching that significantly reduce the memory bandwidth requirement for video data. Software decoding of MPEG-4 video data generates much more cache-memory traffic than required. Proper understanding of the decoding algorithm and the composition of its data set is obvious to improve the performance of such a system. The focus of this paper is cache modeling and optimization for portable communication devices running MPEG-4 video decoding algorithm. The architecture we simulate includes a digital signal processor (DSP) for running the MPEG-4 decoding algorithm and a memory system with two levels of caches. We use VisualSim and Cachegrind simulation tools to optimize cache sizes, levels of associativity, and cache levels for a portable device decoding MPEG-4 video. Abu Asaduzzaman is, currently, a PhD candidate in the department of Computer Science and Engineering (CSE), Florida Atlantic University (FAU), Boca Raton, Florida. He received his MS degree in computer engineering from FAU in 1997. Mr. Asaduzzaman worked for ECI Telecom as a software engineer from 1998 to 2001. From 2001 to 2003, he worked for BlueCross and BlueShield of Florida and SunPass (FDoT) as an IT Consultant. Currently, he is working as a research assistant at CSE Dept, FAU. His research interests include cache optimization, architecture exploration, embedded system evaluation, and networks-on-a-chip (NoC). He has published several research papers in these areas. Abu is a member of the honor society of Phi Kappa Phi, Tau Beta Pi, Upsilon Phi Epsilon, and the Association for Computing Machinery (ACM) FAU Chapter. Imad Mahgoub received the MS degree in applied mathematics and MS degree in electrical and computer engineering, both from North Carolina State University, Raleigh in 1983 and 1986 respectively and the PhD degree in computer engineering from the Pennsylvania State University, University Park, PA in 1989. Dr. Mahgoub joined Florida Atlantic University (FAU), Boca Raton, Florida in 1989. Currently he is a full professor of Computer Science and Engineering department and the director of the Mobile Computing Laboratory. His research interests include performance evaluation, mobile computing, sensor networks, and parallel and distributed processing. He has published over 80 research papers in these areas. He is the co-editor of the Mobile Computing Handbook and the Handbook of Sensor Networks. Dr. Mahgoub has served on the program committees of numerous conferences. He has been the vice-chair for the Symposium on Performance Evaluation of Computer and Telecommunication Systems (SPECTS) since 2003. He is a senior member of the IEEE. He is also a member of Tau Beta Pi, Upsilon Pi Epsilon, the IEEE Computer Society, and the ACM.     

供应链中的信息流

企业的信息方面回报（ＲＯＩ）的增加是提高企业竞争力的有效方式之一。企业要设法消除供应链各成员之间信息传递的障碍,以便减少“内耗”,使供应链各成员实现信息共享。供应链中信息的价值不是体现在信息的数量上,而是体现在对信息的强化能力上,体现在各成员从大量有用的信息中发展多少知识。     

The crippled queen placement problem

We describe the outcome of various combinations of choices made by individuals in the solution of a non-trivial combinatorial problem on a computer. The programs which result are analyzed with respect to execution speed, design time, and difficulty in debugging. The solutions obtained vary dramatically as a result of choices made in the overall design of the solution. Choices made at lower levels in the top-down tree of design choices seem to have less effect on the parameters analyzed. A tradeoff between mathematical effort in algorithm design, and program speed is evident, since some solutions required solution-time which grows exponentially with the case size, while another solution presented here gives a closed-form expression for the required answers for all large cases.     

A Combined Interleaving Technique for Trellis Coded MPSK Systems in Rayleigh Fading Channels

Freedom of mobility is the latesttrend in the evolution of digital communicationsystems. In these systems bandwidth and powerconstraints limit the mobility of the users. TCM(trellis coded modulation) is a combined coding andmodulation scheme which increases the productivity ofa digital communication system without increasing thetransmitted power or the required bandwidth. A mobilecommunication channel is affected from noise andfading because of the multipath propagation. On aRayleigh fading channel, coding should be used withtechniques which uncorrelate the received energy ofeach consecutive coded symbol. Interleaving is one ofthese techniques and used to make burst errors intorandom errors which can be corrected by errorcorrecting codes. In this paper, the trellis codingsystem which combines a regular convolutional encoder,bit interleaver, coordinate interleaver, and anappropriate decoder is considered. The analytical biterror probability upper bounds are derived for the8-PSK TCM system whose diversity is increased by usinga regular 2/3 rate convolutional code followed bythree bit interleavers and a 8-PSK signal mapperfollowed by two coordinate interleavers. Theanalytical and simulation results show that toincrease the diversity of the trellis coded M-PSKsystems in Rayleigh fading channels is the primary keyfor reliable transmission of high quality voice anddigital data.     

Low complexity radix-4 butterfly design for the soft-decision Viterbi decoder

This study presents a new radix-4 butterfly design for Viterbi decoders. The branch symmetry of the proposed radix-4 butterfly is exploited to design a low-complexity radix-4 butterfly module to simplify the implementation of the soft-decision Viterbi decoder. By exploiting the branch symmetry, only a half of branch metrics need to be computed, while other metrics can be derived from the computed branches. Therefore, the branch metric computation of the radix-4 butterfly can be reduced by a factor of 2. Considering the convolutional code in the DAB system as an example, experimental results indicate that the proposed radix-4 butterfly design can reduce the number of FPGA slices of the radix-4 butterfly module by 24% over the conventional design.