Model‐based code generation for HLA federates

This paper addresses the problem of automated code generation for a High Level Architecture compliant federate application given its behavior model. The behavior model is a part of the architectural model of a federation that the federate can participate in. The federate behavior model is based on Live Sequence Charts, adopted as the behavioral specification formalism in the Federation Architecture Metamodel (FAMM). FAMM serves as a formal language for describing federation architectures. An objective is to help the testing of federation architecture by means of its prototype implementation early in the development lifecycle. A further objective is to help developers construct complete federate applications that are well modularized. The approach to achieve these objectives is aspect‐oriented in that the generated code, which handles the federate's interactions with a federation execution, serves as the base code, where the computation logic is to be weaved as an aspect. Copyright © 2009 John Wiley & Sons, Ltd.     

一个关于程序时间性质的验证框架

运行时间是计算机程序的重要性质之一。对于运行时间而言,常用的时间复杂度分析技术基于的是抽象的算法,并非实际程序。而对于实际程序,大多数程序验证技术则不适合验证运行时间。提出一个运行时间的验证框架以解决这个问题,该框架适用于实际代码,而同时和复杂度分析一样,具有编程语言无关性。在对运行时间的性质要求较高的场合下,可以用于提高软件的可靠性。     

基于MSP430的二线制高精度表头设计

针对传统的二线制表头在高温下测量精度差、温漂大的特点,提出了一种在高温下的高精度数显表头的设计方案。分别介绍了其软硬件的实现方法,即采用超低功耗微处理器MSP430F4250采集回路中的电流值,采用24位ADC转换器ADS1244进行模数转换,最后将经过运算的变送器输出信号值在LED数码管中加以显示。实测结果证明,该表头在高温下测量精度高、工作可靠、抗干扰性强、实用性强,势必会成为无源二线制仪表的发展方向。     

2009多国仪器仪表展览会流量仪表评估

简要介绍了2009年多国仪器仪表展览会(MICONEX2009)上流量仪表参展商概况、12大类参展流量仪表所占比例,并分析评述了展品及其亮点,如新流量测最原理的激光流量计,向小流量低流速方向延伸的超声流量计、超声热黾表和超声水表,能测量液体的MEMS(微机电系统)制的热式流量计,可代替机械式的MEMS家用/商用燃气表,高阶椭圆齿轮流量计等.     

电压输出型传感器高精度数字转换模块的研制

传感器输出信号的数字采集是工业检测系统数字化的关键技术,通过对各种传感器的分析和研究,采用能适应0～100mV宽动态模拟输入信号范围、24位显示分辨率的数字采集技术,研制出电压输出型传感器高精度数字转换模块.该模块具有功耗低、体积小、可靠性高、使用安装方便的特点,解决了工业现场各种类型传感器输出信号的数字量转换问题,它为企业新产品研发和传统设备数字化改造提供了前端数字信息采集的硬件支持.     

基于工作过程的高职软件课程体系改革的研究与实践

本文探讨了在高职院校中开展软件外包服务的目的和意义,提出组建和管理软件外包服务中心的办法:通过软件外包中心业务的开展,分析软件企业实际的工作过程,根据工作过程深入企业调研,有针对性地了解高职学生能胜任的职业岗位群以及所对应的工作任务和职业能力,与企业技术专家共同制定以工作过程为导向的软件专业课程体系。     

Enhancing integrated earthquake simulation with high performance computing

Integrated earthquake simulation (IES) is a seamless simulation of the three earthquake processes, namely, the earthquake hazard process, the earthquake disaster process and the anti-disaster action process. High performance computing (HPC) is essential if IES, or particularly, the simulation of the earthquake disaster process is applied to an urban area in which 10^4∼6 structures are located. IES is enhanced with parallel computation, and its performance is examined, so that virtual earthquake disaster simulation will be made for a model of an actual city by inputting observed strong ground motion. It is shown that parallel IES has fairly good scalability even when advanced non-linear seismic structure analysis is used.     

基于HLA的防空导弹营火力仿真系统设计

根据当前空防对抗系统的组成及特点,在建立某型防空导弹营火力仿真系统实体模型的基础上,结合以往项目开发经验,简化联邦开发与执行模型,研究基于UML的HLA开发过程,分4步对仿真系统联邦进行设计和实现。针对目前仿真系统可信度校验难度大的问题,构建该仿真系统的可信度评估层次模型,设计一种基于最优传递矩阵和三角模糊数的层次分析法,既可避免人为主观因素的影响,又可保证评估过程高效性。仿真实验结果表明,该系统高效可信,节省训练经费,为防空导弹分队火力单元的部署和作战效能的改进提供辅助决策手段。     

FPGA implementation and performance evaluation of a high throughput crypto coprocessor

This paper describes the FPGA implementation of FastCrypto, which extends a general-purpose processor with a crypto coprocessor for encrypting/decrypting data. Moreover, it studies the trade-offs between FastCrypto performance and design parameters, including the number of stages per round, the number of parallel Advance Encryption Standard (AES) pipelines, and the size of the queues. Besides, it shows the effect of memory latency on the FastCrypto performance. FastCrypto is implemented with VHDL programming language on Xilinx Virtex V FPGA. A throughput of 222 Gb/s at 444 MHz can be achieved on four parallel AES pipelines. To reduce the power consumption, the frequency of four parallel AES pipelines is reduced to 100 MHz while the other components are running at 400 MHz. In this case, our results show a FastCrypto performance of 61.725 bits per clock cycle (b/cc) when 128-bit single-port L2 cache memory is used. However, increasing the memory bus width to 256-bit or using 128-bit dual-port memory, improves the performance to 112.5 b/cc (45 Gb/s at 400 MHz), which represents 88% of the ideal performance (128 b/cc).