ADIC iPlatform智能磁带库体系结构

本文介绍了ADIC iPlatform智能磁带库体系结构。     

关于建立城市智能交通实验研究中心的设想

基于联系国内外智能交通系统研究的具体实际，提出了建立城市智能交通实验研究中心的设想，并结合一个集成了视频和线圈信息采集方式的实验研究中心简单设计方案，对其所具有的基本功能作了初步研究和探讨。该系统兼具促进交流和有关培训等社会职能，可以作为国家智能交通事业发展过程中一种特殊的示范工程。     

Discrete Wavelet Transform: Architectures, Design and Performance Issues

Due to the demand for real time wavelet processors in applications such as video compression [1], Internet communications compression [2], object recognition [3], and numerical analysis, many architectures for the Discrete Wavelet Transform (DWT) systems have been proposed. This paper surveys the different approaches to designing DWT architectures. The types of architectures depend on whether the application is 1-D, 2-D, or 3-D, as well as the style of architecture: systolic, semi-systolic, folded, digit-serial, etc. This paper presents an overview and evaluation of the architectures based on the criteria of latency, control, area, memory, and number of multipliers and adders. This paper will give the reader an indication of the advantages and disadvantages of each design.     

协同作战能力简析

协同作战能力(CEC)是一种充分利用网络技术的新型海岸防空技术，给系统的作战能力带来了革命性的交破。本文对协同作战能力的产生、功能、组成以及未来的发展趋势作了详细的介绍，阐述了CEC系统的总体设计思想。在此基础上，将CEC系统与传统的作战系统的性能和设计思想在各方面进行了比较，交出了CEC系统各方面的优越性能。协同作战能力是现代和未来作战系统的发展方向，CEC系统的发展必将成为衡量各国国防科技现代化的重要指标。     

高炉开炉装料计算软件的设计

高炉开炉装料计算工作繁琐、复杂,手工计算耗费时间长、容易出错,难以得到最佳方案,影响高炉顺利开炉。通过高炉开炉装料计算软件的开发实践,介绍了装料计算模型的建模步骤;讨论了软件的功能需求;阐述了选用三层网络结构的原因,从而描述了装料计算软件的设计方法。软件投入运行后,能够快速、准确地计算、分析开炉数据,取得了满意的效果。     

微机织机监测的巡检系统

本文介绍织机监测的数据采集系统即巡检系统,重点讨论了巡检方案的选择、巡检电路的设计、巡检软件的编制以及几种抗干扰的措施。     

对水轮机自动调速器油压控制电路的改进

YT－1000型油压自动调速器在运行中不能维持正常油压、在不增加任何设备的情况下，只改动二次接线的处理方法，就能消除隐患、解决问题。     

On the Automatic Recovery of Style-Specific Architectural Relations in Software Systems

The cost of maintaining a software system over a long period of time far exceeds its initial development cost. Much of the maintenance cost is attributed to the time required by new developers to understand legacy systems. High-level structural information helps maintainers navigate through the numerous low-level components and relations present in the source code. Modularization tools can be used to produce subsystem decompositions from the source code but do not typically produce high-level architectural relations between the newly found subsystems. Controlling subsystem interactions is one important way in which the overall complexity of software maintenance can be reduced.We have developed a tool, called ARIS (Architecture Relation Inference System), that enables software engineers to define rules and relations for regulating subsystem interactions. These rules and relations are called Interconnection Styles and are definedusing a visual notation. The style definition is used by our tool to infer subsystem-level relations in designs being reverse engineered from source code.In this paper we describe our tool and its underlying techniques and algorithms. Using a case study, we describe how ARIS is used to reverse engineer high-level structural information from a real application.     

Object-oriented DBMS requirements

The requirements on an object-oriented DBMS for management of information in a large, complex enterprise are presented. These requirements aid in the achievement of an environment characterized by data sharing, open architectures, application and data portability, and assurance of data integrity. They were defined from the point of view of a user of the DBMS; therefore they describe the expected functionality of the DBMS and do not specify the method of implementation to achieve this functionality. They encompass requirements on the data model, query and data manipulation languages, the system architecure, interfaces to the system, change management, and transaction management.     

A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception

Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as back-plane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed transmission across long interconnects using multi-valued encoding. Our multi-valued CMOS circuits take advantage of the threshold voltage control of the transistors, by using the signal-voltage-to-threshold-voltage span, in order to make area-efficient implementations of 4-PAM (pulse amplitude modulation) transceivers operating at high speed. In a comparison of a variety of published technologies, for signal transmission with interconnects of 10-15 mm length, we show up to 50% improvement in energy for on-chip signal transmission over binary encoding together with higher limits for operating speeds without a penalty in circuit noise margin.