FPGA实现RS-422通信的一种改进方法

给出了一种FPGA实现RS-422通信的改进方法。通过实例,介绍了传统的及改进后的FPGA实现RS-422通信的硬件和软件实现方法,改进后的方法硬件实现只需要FP-GA和差分线路驱动器,芯片使用种类少,印制板面积小,软件接口也较传统方法简单,降低了开发成本。     

智能跟踪系统中目标阴影消除算法的研究与应用

研究了阴影消除算法在基于DSP处理器的智能跟踪系统中的应用。在应用中加入了快速填充与噪声消除算法以提高阴影消除的准确性。为了提高系统的实时性,对于阴影消除又采取了一定的优化措施。这些方法适用于有流水线处理特征的微控制器和微处理器。实验表明,这种方法能够实现高速运转且可以有效地减少CPU占用率。     

新型数字式频率电压紧急控制装置设计

提出了一种基于MCU+DSP结构的频率电压紧急控制装置设计方案,通过测量系统频率和电压自动分级投切负荷或解列机组以保证电力系统的功率缺额在最小程度。利用双电压回路进行电压测量,提高可靠性,采用硬件测频,同时为了保证测量的精度和实时性,采用一种新型的频率测量算法实现软件频率测量,算法简单,所需数据窗少。对故障的判断和决策采用多条件、多重闭锁机制,有效防止误动和拒动。     

达芬奇视频处理系统中的加解密平台

本文介绍了一种应用于TI达芬奇视频处理系统的加解密平台,首先对该平台相关的硬件结构做了介绍，然后对其所采用的加解密算法做了简要说明。     

基于DSP的通用测井信号数据采集接口板

阐述了测井仪器信号的多样性，地面仪具有较强兼容性的必要性，以及DSP应用于测井信号数据采集的可行性。介绍了基于DSP的通用测井信号数据采集接口板的工作原理、软件流程及其应用领域。     

DSP技术的创新发展和应用

本文结合理论分析了DSP较传统处理器的创新性,阐述了DSP在当下应用领域和市场前景应用情况,加以说明在当今数字化时代背景下,DSP已成为通信、计算机、消费类电子产品等领域的基础器件。     

外辐射源雷达实验系统中高速实时数字脉冲压缩的实现

针对外辐射源雷达实验系统中随机大时宽连续波回波信号的低频域占空比特点，对传统脉压算法进行简化处理，并采用以多片通用DSP芯片ADSP21060为核心建立处理机平台．设计并实现了一个高效的高速相干连续波雷达时域数字脉冲压缩子系统。     

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modify the controller to interpret some of the instructions differently only within the initial test mode. In this paper, we have proposed a fuctional self-test methodology that is deterministic in nature. In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests. We first start with testing processor core using our proposed architedture. Once the testing of the processor core is completed, this core is used to test the embedded SRAMs. A test algorithm which utilizes a mixture of existing memory testing techniques and covers all important memory faults is presented in this paper. The proposed memory test algorithm covers 100% of the faults under the fault model plus a data retention test. The hardware overhead in the proposed architecture is shown to be negligible. This architecture is implemented on UTS-DSP (University of Tehran and Iran Communicaton Industries (SAMA)) IC which has been designed in VLSI Circuits and Systems Laboratory.     

Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications

The iteration space of a loop nest is the set of all loop iterations bounded by the loop limits. Tiling the iteration space can effectively exploit the available parallelism, which is essential to multiprocessor compiling and pipelined architecture design. Another improvement brought by tiling is the better data locality that can dramatically reduce memory access and, consequently, the relevant memory access energy consumptions. However, previous studies on tiling were based on the data dependence, thus arrays without dependencies such as input arrays (data streams) were not considered. In this paper, we extend the tiling exploration to also accommodate those dependence-free arrays, and propose a stream-conscious tiling scheme for off-chip memory access optimization. We show that input arrays are as important, if not more, as the arrays with data dependencies when the focus is on memory access optimization instead of parallelism extraction. Our approach is verified on TI’s low power C55X DSP with popular multimedia applications, exhibiting off-chip memory access reduction by 67% on average over the traditional iteration space tiling.