张南垣的生平、家族与交游——乔莱《张处士墓志铭》考略

造园大师张南垣是中国园林史研究的重要课题,已有大量的相关资料和论著。乔莱《张处士墓志铭》的发现提供了张南垣研究的核心材料,极大地推进了这一研究。采用史源学和年代学方法,根据《张处士墓志铭》提供的线索,考证了作者乔莱与张氏家族的交往,推断张南垣名“琏”而非“涟”,祖籍为松江华亭县,梳理了张南垣的家学传承与造园历程、张南垣的先辈与子孙谱系、张南垣的交游等内容。有助于深入认识张南垣的造园成就,完善更新张南垣研究的框架,进而剖析古代造园背后的家族、社会和文化等层面的运行机制。     

论传统汉字设计的文人意匠

对汉字的装饰美化几乎是所有中国古代文人的追求。中国古代充满文人意味的汉字设计主要体现在书法文字、花押签名以及诗文创作等方面,传统汉字设计体现了古代文人的智慧与灵性,倾注了古代文人的思想和情趣。通过对其文人意匠的研究,可以帮助现代文字设计师充分认识现代设计中文人意味的缺失,并从传统设计中寻求有益的启示。     

High quality relaxed Ge layers grown directly on a Si(0 0 1) substrate

After a long period of developing integrated circuit technology through simple scaling of silicon devices, the semiconductor industry is now embracing technology boosters such as strain for higher mobility channel material. Germanium is the logical supplement to enhance existing technologies, as its material behaviour is very close to silicon, and to create new functional devices that cannot be fabricated from silicon alone (Hartmann et al. (2004) [1]). Germanium wafers are, however, both expensive and less durable than their silicon counterparts. Hence it is highly desirable to create a relaxed high quality Ge layer on a Si substrate, with the provision that this does not unduly compromise the planarity of the system. The two temperature method, proposed by Colace et al. (1997) [2], can give smooth (RMS surface roughness below 1 nm) and low threading dislocation density (TDD <10⁸ cm⁻²) Ge layers directly on a Si(0 0 1) wafer (Halbwax et al. (2005) [3]), but these are currently of the order of 1-2 μm thick (Hartmann et al. (2009) [4]).We present an in depth study of two temperature Ge layers, grown by reduced pressure chemical vapour deposition (RP-CVD), in an effort to reduce the thickness. We report the effect of changing the thickness, of both the low temperature (LT) and the high temperature (HT) layers, emphasising the variation of TDD, surface morphology and relaxation.Within this study, the LT Ge layer is deposited directly on a Si(0 0 1) substrate at a low temperature of 400 °C. This low temperature is known to generate monolayer islands (Park et al. (2006) [5]), but is sufficiently high to maintain crystallinity whilst keeping the epitaxial surface as smooth as possible by suppressing further island growth and proceeding in a Frank-van der Merwe growth mode. This LT growth also generates a vast number of dislocations, of the order of 10⁸-10⁹ cm⁻², that enable the next HT step to relax the maximum amount of strain possible. The effect of varying the HT layer thickness is studied by depositing on a LT layer of fixed thickness (100 nm) at a higher growth temperature of 670 °C. We find that the HT layer allows Ge-on-Ge adatom transport to minimise the surface energy and smooth the layer. The final step to the technique is annealing at a high temperature that allows the dislocations generated to glide, increasing the degree of relaxation, and annihilate. We find that annealing can reduce the TDD to the order of 10⁷ cm⁻², but at a cost of a significantly roughened surface.     

Introduction of local tensile strain on Ge substrates by SiGe stressors selectively grown on wet chemically recessed regions for strained Ge-nMOSFETs

Introduction of tensile strain into Ge substrates was demonstrated by forming embedded SiGe stressors on the recessed regions formed by an anisotropic wet chemical etching process for strained Ge-nMOSFETs having high electron mobility. A damage-free and well controlled anisotropic wet chemical etching process is developed in order to avoid plasma-induced damages in a conventional RIE process. The uni-axial tensile strain over 1% near the Ge recess-edge regions, which is induced by the embedded SiGe stressors, is also demonstrated for the first time. These results suggest that higher electron mobility than the upper-limit for a Si-MOSFET is obtainable in short channel strained Ge-nMOSFETs with the embedded SiGe stressors.     

Effective passivation of defects in Ge-rich SiGe-on-insulator substrates by Al2O3 deposition and subsequent post-annealing

A method of Al₂O₃ deposition and subsequent post-deposition annealing (Al₂O₃-PDA) was proposed to passivate electrically active defects in Ge-rich SiGe-on-insulator (SGOI) substrates, which were fabricated using Ge condensation by dry oxidation. The effect of Al₂O₃-PDA on defect passivation was clarified by surface analysis and electrical evaluation. It was found that Al₂O₃-PDA could not only suppress the surface reaction during Al-PDA in our previous work [Yang H, Wang D, Nakashima H, Hirayama K, Kojima S, Ikeura S. Defect control by Al-deposition and the subsequent post-annealing for SiGe-on-insulator substrates with different Ge fractions. Thin Solid Films 2010; 518: 2342-5.], but could also effectively passivate p-type defects generated during Ge condensation. The concentration in the range of 10¹⁶-10¹⁸ cm⁻³ for defect-induced acceptors and holes in Ge-rich SGOI drastically decreased after Al₂O₃-PDA. As a result of defect passivation, the electrical characteristics of both back-gate p-channel and n-channel metal-oxide-semiconductor field-effect transistors fabricated on Ge-rich SGOI were greatly improved after Al₂O₃-PDA.     

SiGe异质结双极晶体管的基区优化

对应用于高频微波功率放大器的SiGe异质结双极晶体管(HBT)的基区进行了优化.研究发现,器件对基区Ge组分以及掺杂浓度十分敏感.采用重掺杂基区,适当提高Ge组分并形成合适的浓度分布,可以有效地改进SiGe HBT的直流特性,同时能够提高器件的特征频率.晶体管主要性能的提高使SiGe HBT技术在微波射频等高频电子领域得到更加广泛的应用.     

改善SiGe HBTs热稳定性的Ge组分分布优化与设计

The impact of the three state-of-the-art germanium(Ge) profiles(box,trapezoid and triangular) across the base of SiGe heterojunction bipolar transistors(HBTs) under the condition of the same total amount of Ge on the temperature dependence of current gainβand cut-off frequency f_T,as well as the temperature profile,are investigated.It can be found that although theβof HBT with a box Ge profile is larger than that of the others,it decreases the fastest as the temperature increases,while theβof HBT with a triangular Ge profile is smaller than that of the others,but decreases the slowest as the temperature increases.On the other hand,the f_T of HBT with a trapezoid Ge profile is larger than that of the others,but decreases the fastest as the temperature increases,and the f_T of HBT with a box Ge profile is smaller than that of the others,but decreases the slowest as temperature increases.Furthermore,the peak and surface temperature difference between the emitter fingers of the HBT with a triangular Ge profile is higher than that of the others.Based on these results,a novel segmented step box Ge profile is proposed,which has modestβand f_T,and trades off the temperature sensitivity of current gain and cut-off frequency,and the temperature profile of the device.     

Nickel-containing nano-sized islands grown on Ge(111)-c(2 × 8) and Ag/Ge(111)-(√3 × √3) surfaces

The formation of nano-islands on both a Ge(111)-c(2 × 8) surface and an Ag/Ge(111)-(√3 × √3) surface evaporated with 0.1 ML Ni was investigated by scanning tunneling microscopy (STM). We have noticed that at temperatures lower than 670 K, the reaction between Ni and the individual substrate surfaces proceeds to form different structures: flat-topped islands with a 2√7 × 2√7 or a 3 × 3 reconstruction on the Ni/Ge(111)-c(2 × 8) surface vs. islands with a 7 × 7 reconstruction on the Ni/Ag/Ge(111)-(√3 × √3) surface. From this we have inferred that within a temperature range between room temperature and 670 K, the intermediate Ag layer retards mixing between Ni and Ge atoms. As a result, the grown islands are composed of pure Ni atoms. Within a temperature range from 670 to 770 K, most islands produced on the Ag/Ge(111)-(√3 × √3) surface are identical with those formed on the Ni/Ge(111)-c(2 × 8) surface, suggesting that above 670 K, Ni atoms are likely to bind with Ge atoms. However, an essential difference between STM images of the surfaces under study exists in the appearance of large elongated islands on the Ni/Ag/Ge(111)-(√3 × √3) surface. The formation of the latter is explained in terms of a difference in energy for Ni diffusion on the Ge(111)-c(2 × 8) and Ag/Ge(111)-(√3 × √3) surfaces.     

Resistive switching memory characteristics of Ge/GeOx nanowires and evidence of oxygen ion migration

The resistive switching memory of Ge nanowires (NWs) in an IrO_x/Al₂O₃/Ge NWs/SiO₂/p-Si structure is investigated. Ge NWs with an average diameter of approximately 100 nm are grown by the vapor–liquid-solid technique. The core-shell structure of the Ge/GeO_x NWs is confirmed by both scanning electron microscopy and high-resolution transmission electron microscopy. Defects in the Ge/GeO_x NWs are observed by X-ray photoelectron spectroscopy. Broad photoluminescence spectra from 10 to 300 K are observed because of defects in the Ge/GeO_x NWs, which are also useful for nanoscale resistive switching memory. The resistive switching mechanism in an IrO_x/GeO_x/W structure involves migration of oxygen ions under external bias, which is also confirmed by real-time observation of the surface of the device. The porous IrO_x top electrode readily allows the evolved O₂ gas to escape from the device. The annealed device has a low operating voltage (<4 V), low RESET current (approximately 22 μA), large resistance ratio (>10³), long pulse read endurance of >10⁵ cycles, and good data retention of >10⁴ s. Its performance is better than that of the as-deposited device because the GeO_x film in the annealed device contains more oxygen vacancies. Under SET operation, Ge/GeO_x nanofilaments (or NWs) form in the GeO_x film. The diameter of the conducting nanofilament is approximately 40 nm, which is calculated using a new method.     

侧墙技术在相变存储器中的应用

从相变存储器(phase change random access memory,PCRAM)的基本结构和工作原理出发,首先介绍了PCRAM的技术优势、面临的技术挑战、常用的解决策略以及存在的相应问题;接着阐述了在微电子加工中广泛应用的关键工艺——侧墙技术,并将其在PCRAM中的应用成果进行了分类;然后从加热电极的制备、相变材料限制结构的制备、新相变材料的制备与表征和器件间互联等4个方面展开叙述;最后展望了该技术在相变存储领域应用发展的趋势。侧墙技术因其具备自对准的特点,制备工艺可控性好,制备精度不依赖于光刻精度,在纳米技术飞速发展的今天,侧墙技术将会在更高精度上发挥其作用。