Effects of self-aligned electroplating Cu pillar/Sn-xAg bump on dense Al lines for chip-to-package connection

Self-aligned electroplating is applied to form the Cu pillar/Sn-Ag bump for semiconductor device packaging, while passivation SiN cracks are usually observed at the bump edge on the bump of the array (BOA). In this paper, the simulation method was used to investigate the mechanism of SiN cracks and then, the bump process was optimized to improve the mechanical properties of the Cu pillar/Sn-Ag bump. It was found that higher reflow rounds could improve the shear strength due to the large degree of contact between the rugged scallop-like shape of the Cu₆Sn₅ and the Sn-Ag solder. The fracture plane cleaved between the Sn-Ag and Cu₆Sn₅ interface is consistent with the simulation results. The hardness of the Sn‒Ag solder is proportional to the reflow rounds, and the amount of Ag₃Sn phase precipitation within the Sn-Ag solder contributes to the hardness value. In contrast, the disadvantage is that thermal residual stress could deteriorate the SiN crack, especially for a BOA structure The study concludes that an optimal bump process, including Sn-2%Ag solders at 260 °C for 30 s, could obtain a high shear strength and appropriate solder hardness without passivated SiN cracking.     

Thermal analysis for fast thermal-response Si waveguide wrapped by SiN

A new type of Si waveguide wrapped by silicon nitride (SiN) is designed,and its optical and thermal analysis are presented.The thickness of SiN up-cladding should be larger than 1 μm in order to preven...     

Development of a novel tool for semiconductor process control

A collaborative project between the Surrey Ion Beam Centre and the positron beam group at the University of Bath is developing a bench-top positron tool suitable for use in the semiconductor industry. The technique's non-destructive nature, coupled with its high sensitivity to defects, makes it a potentially ideal method for detecting process problems at an early stage. Measurements on the existing laboratory-based system have shown, for example, a high sensitivity to variations in parameters such as temperature in the growth of epitaxial layers. An instrument suitable for use in the fabrication environment is described, together with diagnostic studies of PECVD-deposited SiN layers, of thicknesses in the range 21–133 nm, performed in conjunction with ellipsometric and RBS measurements. The technique is sensitive to the atomic composition of the SiN epilayers and, in conjunction with ellipsometry, is able to measure the density of the layers and to quantify the densification on annealing at 900°C.     

SiN/bamboo like carbon nanotube composite electrodes for lithium ion rechargeable batteries

A dual stage technique employing hot filament chemical vapor deposition (HFCVD) and radio frequency sputtering was used to synthesize SiN/BCNTs (bamboo like carbon nanotubes) on copper substrates. The films were characterized by scanning electron microscopy (SEM), transmission electron microscopy (TEM), Raman spectroscopy, X-ray photoelectron spectroscopy (XPS), Electron field emission studies (EFE), charge-discharge, and cyclic voltammetry. The comprehensive characterization is consistent with a nanolayer of amorphous SiN on BCNTs. Field emission experiments confirm the excellent contact of the SiN nanolayer with the surface of the BCNTs necessary for fabrication of a coin cell. Electrochemical testing shows that SiN/BCNT electrode can deliver an initial discharge capacity of 2000 mAh g⁻¹ which is higher than the capacity of graphite and the reversible capacity after ten cycles is 300 mAh g⁻¹. The cyclic voltammetry results suggest good reversibility with Li during cycling.     

High selectivity (SiN/SiO2) etching using an organic solution containing anhydrous HF

An etching process with high selectivity for SiN relative to SiO₂ at a low temperature is required for an etching process in LSI process. We achieved SiN film etching with high selectivity using an organic solvent (ethylene glycol dimethyl ether) containing anhydrous hydrogen fluoride. Selectivity as high as 15 was obtained at 80 °C. It was found that anhydrous HF effectively induces high selectivity for SiN relative to SiO₂. SiN film etching with high selectivity performed at low temperature for a single wafer process can be readily applied to future node technology devices.     

Influence of silane flow on MOVPE grown GaN on sapphire substrate by an in situ SiN treatment

In this paper, the influence of silane flow on metalorganic vapour phase epitaxy (MOVPE) grown GaN on sapphire substrate by an in situ SiN treatment has been investigated. A flow of 10 sccm with treatment duration of 120 s appears to be the optimal value and improves the crystal quality. The dislocation density, determined by atomic force microscopic (AFM), is as low as 5×10⁸ cm⁻². A reduction of I₂ full width at half maximum (FWHM) to 4 meV and an increase of both BE/YL and BE/DAP intensity ratio are also obtained.     

Fabrication and characterization of high performance AlGaN/GaN HEMTs on sapphire with silicon nitride passivation

AlGaN/GaN high electron mobility transistors(HEMTs)with high performance were fabricated and characterized.A variety of techniques were used to improve device performance,such as AlN interlayer,silicon nitride passivation,high aspect ratio T-shaped gate,low resistance ohmic contact and short drain-source distance. DC and RF performances of as-fabricated HEMTs were characterized by utilizing a semiconductor characterization system and a vector network analyzer,respectively.As-fabricated devices exhibited a maximum drain current density of 1.41 A/mm and a maximum peak extrinsic transconductance of 317 mS/mm.The obtained current density is larger than those reported in the literature to date,implemented with a domestic wafer and processes.Furthermore, a unity current gain cut-off frequency of 74.3 GHz and a maximum oscillation frequency of 112.4 GHz were obtained on a device with an 80 nm gate length.     

Characterisation of micrometre-sized inversion layer emitters in crystalline Si

The electrical properties of micrometre-sized inversion-layer (IL) emitters in crystalline Si are investigated by measuring their current–voltage characteristics using a so-called NOSFET device. The IL emitter is induced by a SiN/SiO double-layer stack. We show that by scanning the surface with a negatively biased tip, the IL emitter below the tip can be controllably eliminated.     

Si含量对TiAlSiN纳米复合涂层的微观结构和力学性能的影响

采用不同Si含量的TiAlSi复合靶,在Si基底片上用射频磁控溅射工艺沉积了TiAlSiN纳米复合涂层,采用X射线衍射仪(XRD)、高分辨透射电子显微镜(HRTEM)和纳米压痕技术研究了Si含量对TiAlSiN涂层的微观结构和力学性能的影响.结果表明:TiAlSiN涂层内部形成了Si3N4界面相包裹TiAlN纳米等轴晶粒的纳米复合结构.随着Si含量的增加,TiAlSiN涂层的结晶程度先增加后降低,涂层内部的晶粒尺寸先减小后趋于平稳,涂层的力学性能先升高后降低.当Si与TiAl原子比为3∶22时获得的最高硬度和弹性模量分别为37.1GPa和357.3 GPa.     

Development of metal etch mask by single layer lift-off for silicon nitride photonic crystals

We present a method for fabrication of nanoscale patterns in silicon nitride (SiN) using a hard chrome mask formed by metal liftoff with a negative ebeam resists (maN-2401). This approach enables fabrication of a robust etch mask without the need for exposing large areas of the sample by electron beam lithography. We demonstrate the ability to pattern structures in SiN with feature sizes as small as 50 nm. The fabricated structures exhibit straight sidewalls, excellent etch uniformity, and enable patterning of nanostructures with very high aspect ratios. We use this technique to fabricate two-dimensional photonic crystals in a SiN membrane. The photonic crystals are characterized and shown to have quality factors as high as 1460.