高分辨率地震资料处理中的优化速度分析方法

速度分析是地震资料处理过程中的重要一环。速度分析的质量直接影响动静校正,继而影响叠加成像以及偏移归位。针对如何优化速度分析,提出了基于道集资料噪音衰减、道集内相位时差校正、道集优化处理以及速度拾取应用约束等过程的优化速度分析方法。该方法在实际资料处理中取得了很好的效果。     

基于VXI总线的超宽带线性调频信号源的设计

主要介绍了VXI总线C尺寸超宽带线性调频信号源的设计方法，重点描述了利用现场可编程逻辑器件FPAG和DSP设计VXI总线接口电路，以及数字波形存储直读技术在线性调频信号源中的应用。     

基于Gabor展开的水下目标激光探测的信号检测与识别

针对水下目标激光探测的信号检测与识别的问题 ,通过对回波信号的Gabor展开进行分析 ,建立了局部窗口多重相关的峰值检测方法 ,以及利用系数矩阵的迹和特征值描述目标的反射性能 ,实现了对目标的分类识别。实验表明 ,上述方法对目标的有效检测率达 93 0 % ,分类识别有效率达 83 2 %。     

基于CAN总线的舵机控制系统设计

主要介绍了一种基于CAN总线的舵机控制系统。系统以CAN总线作为通信方式，PWM控制信号通过硬件方式产生，具有结构简单、信号稳定和实时性强的特点。     

Discrete Wavelet Transform: Architectures, Design and Performance Issues

Due to the demand for real time wavelet processors in applications such as video compression [1], Internet communications compression [2], object recognition [3], and numerical analysis, many architectures for the Discrete Wavelet Transform (DWT) systems have been proposed. This paper surveys the different approaches to designing DWT architectures. The types of architectures depend on whether the application is 1-D, 2-D, or 3-D, as well as the style of architecture: systolic, semi-systolic, folded, digit-serial, etc. This paper presents an overview and evaluation of the architectures based on the criteria of latency, control, area, memory, and number of multipliers and adders. This paper will give the reader an indication of the advantages and disadvantages of each design.     

复合材料手动扫描超声特征成像检测

研究了复合材料手动扫描超声特征成像检测，通过对超声检测信号的全波列采集与处理，实现了A，B，C扫描成像；相位特征成像；当量特征成像；超声层析技术和超声频谱分析技术。该系统已经在复合材料的检测上得到了良好的应用。     

测量光纤放大器小信号增益谱的一种简便方法

提出了一种用小功率宽带光源较精确测量光纤放大器小信号增益谱的方法。数值模拟表明 ,该方法是完全可行的 ,并且实验结果与数值模拟结果一致。该方法具有简便、易操作的特点。     

一种通用型的目标数据仿真

给出了一种通用型的雷达目标模拟器 ,它能够方便直观的产生各种特征的三维目标轨迹 ,可实时离散出目标点迹 ,为雷达数据处理及精度分析提供数据来源。目标轨迹由一组特征点定义 ,修改方便 ,应用灵活     

Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic

Currently there are design barriers inhibiting the implementation of high-precision digital signal processing (DSP) objects with field programmable logic (FPL) devices. This paper explores overcoming these barriers by fusing together the popular distributed arithmetic (DA) method with the residue number system (RNS) for use in FPL-centric designs. The new design paradigm is studied in the context of a high-performance filter bank and a discrete wavelet transform (DWT). The proposed design paradigm is facilitated by a new RNS accumulator structure based on a carry save adder (CSA). The reported methodology also introduces a polyphase filter structure that results in a reduced look-up table (LUT) budget. The 2C-DA and RNS-DA are compared, in the context of a FPL implementation strategy, using a discrete wavelet transform (DWT) filter bank as a common design theme. The results show that the RNS-DA, compared to a traditional 2C-DA design, enjoys a performance advantage that increases with precision (wordlength).