Discrete Wavelet Transform: Architectures, Design and Performance Issues

Due to the demand for real time wavelet processors in applications such as video compression [1], Internet communications compression [2], object recognition [3], and numerical analysis, many architectures for the Discrete Wavelet Transform (DWT) systems have been proposed. This paper surveys the different approaches to designing DWT architectures. The types of architectures depend on whether the application is 1-D, 2-D, or 3-D, as well as the style of architecture: systolic, semi-systolic, folded, digit-serial, etc. This paper presents an overview and evaluation of the architectures based on the criteria of latency, control, area, memory, and number of multipliers and adders. This paper will give the reader an indication of the advantages and disadvantages of each design.     

协同作战能力简析

协同作战能力(CEC)是一种充分利用网络技术的新型海岸防空技术，给系统的作战能力带来了革命性的交破。本文对协同作战能力的产生、功能、组成以及未来的发展趋势作了详细的介绍，阐述了CEC系统的总体设计思想。在此基础上，将CEC系统与传统的作战系统的性能和设计思想在各方面进行了比较，交出了CEC系统各方面的优越性能。协同作战能力是现代和未来作战系统的发展方向，CEC系统的发展必将成为衡量各国国防科技现代化的重要指标。     

高炉开炉装料计算软件的设计

高炉开炉装料计算工作繁琐、复杂,手工计算耗费时间长、容易出错,难以得到最佳方案,影响高炉顺利开炉。通过高炉开炉装料计算软件的开发实践,介绍了装料计算模型的建模步骤;讨论了软件的功能需求;阐述了选用三层网络结构的原因,从而描述了装料计算软件的设计方法。软件投入运行后,能够快速、准确地计算、分析开炉数据,取得了满意的效果。     

On the Automatic Recovery of Style-Specific Architectural Relations in Software Systems

The cost of maintaining a software system over a long period of time far exceeds its initial development cost. Much of the maintenance cost is attributed to the time required by new developers to understand legacy systems. High-level structural information helps maintainers navigate through the numerous low-level components and relations present in the source code. Modularization tools can be used to produce subsystem decompositions from the source code but do not typically produce high-level architectural relations between the newly found subsystems. Controlling subsystem interactions is one important way in which the overall complexity of software maintenance can be reduced.We have developed a tool, called ARIS (Architecture Relation Inference System), that enables software engineers to define rules and relations for regulating subsystem interactions. These rules and relations are called Interconnection Styles and are definedusing a visual notation. The style definition is used by our tool to infer subsystem-level relations in designs being reverse engineered from source code.In this paper we describe our tool and its underlying techniques and algorithms. Using a case study, we describe how ARIS is used to reverse engineer high-level structural information from a real application.     

Object-oriented DBMS requirements

The requirements on an object-oriented DBMS for management of information in a large, complex enterprise are presented. These requirements aid in the achievement of an environment characterized by data sharing, open architectures, application and data portability, and assurance of data integrity. They were defined from the point of view of a user of the DBMS; therefore they describe the expected functionality of the DBMS and do not specify the method of implementation to achieve this functionality. They encompass requirements on the data model, query and data manipulation languages, the system architecure, interfaces to the system, change management, and transaction management.     

A VLSI architecture for a half-edge-based corner detector

Corner detection is a low-level feature detection operator that is of great use in image processing applications, for example, optical flow and structure from motion by image correspondence. The detection of corners is a computationally intensive operation. Past implementations of corner detection techniques have been restricted to software. In this paper we propose an efficient very large-scale integration (VLSI) architecture for detection of corners in images. The corner detection technique is based on the half-edge concept and the first directional derivative of Gaussian. Apart from the location of the corner points, the algorithm also computes the corner orientation and the corner angle and outputs the edge map of the image. The symmetrical properties of the masks are utilized to reduce the number of convolutions effectively, from eight to two. Therefore, the number of multiplications required per pixel is reduced from 1800 to 392. Thus, the proposed architecture yields a speed-up factor of 4.6 over conventional convolution architectures. The architecture uses the principles of pipelining and parallelism and can be implemented in VLSI.     

百年欧式俱乐部——汉口西商跑马场调查纪实

通过对汉口西商跑马场的调查，说明它移植武汉的经过和历程，以及它在建筑设计方面的一些特点。     

Grouped Approach for the Design of H.264/AVC Motion Estimation Architectures

This letter presents a novel approach for organizing computational resources into groups within H.264/AVC motion estimation architectures, leading to reductions of up to 75% in the equivalent gate count with respect to state‐of‐the‐art designs.     

关于本地传输网网络优化的探讨

根据长期工作经验,对现有网络存在的问题进行分析,提出对本地传输网网络优化的有关建议。     

西方现代建筑设计中的系统方法论

探讨了系统理论在现代建筑设计方法论中的发展过程，并对建筑设计的几个研究方向作概要分析。