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31.
长期以来,FIR数字滤波器大多是在频域上实现。因为,在时域上实现FIR数字滤波所遇到的首要问题,是输入信号序列与冲激响应序列的卷积运算速度难以提高。然而,随着超大规模集成电路的飞速发展,硬件集成度与运算速度获得极大的改观,在时域上实现FIR数字滤波已成为可能。IMSA100是高速、高精度32级数字信号处理器,是完成卷积运算的理想器件。本文论证了用IMSA100实现时域FIR数字滤波器的可行性和硬件设计中的一些问题,并给出了应用举例。在设计中选用8031单片机做主控器,大大提高了性能价格比,使这一设计具有很高的实用价值。 相似文献
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Design and Implementation of a Flexible Manufacturing Control System Using Neural Network 总被引:1,自引:0,他引:1
Magdy M. Abdelhameed Farid A. Tolbah 《International Journal of Flexible Manufacturing Systems》2002,14(3):263-279
Design and implementation of a sequential controller based on the concept of artificial neural networks for a flexible manufacturing system are presented. The recurrent neural network (RNN) type is used for such a purpose. Contrary to the programmable controller, an RNN-based sequential controller is based on a definite mathematical model rather than depending on experience and trial and error techniques. The proposed controller is also more flexible because it is not limited by the restrictions of the finite state automata theory. Adequate guidelines of how to construct an RNN-based sequential controller are presented. These guidelines are applied to different case studies. The proposed controller is tested by simulations and real-time experiments. These tests prove the successfulness of the proposed controller performances. Theoretical as well as experimental results are presented and discussed indicating that the proposed design procedure using Elman's RNN can be effective in designing a sequential controller for event-based type manufacturing systems. In addition, the simulation results assure the effectiveness of the proposed controller to outperform the effect of noisy inputs. 相似文献
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Sung-Eun Lee 《Journal of Stored Products Research》2002,38(2):157-166
The fumigant toxicities of lavender and ylang-ylang essential oils were tested against a chlorpyrifos-methyl resistant strain (QVOS102) and an insecticide-susceptible reference strain (VOS48) of the saw-toothed grain beetle, Oryzaephilus surinamensis L. (Coleoptera: Silvanidae). The resistant strain showed 1.3- and 1.6-fold higher tolerance against lavender and ylang-ylang fumigation toxicity, respectively, relative to the susceptible strain. LT50 values calculated as the time to attain 50% mortality of tested insects during fumigation were determined at two different concentrations. At 15 μl/l of air, QVOS102 had 2.9- and 1.4-fold higher LT50 values for lavender and ylang-ylang fumigation toxicity, respectively, than VOS48. At 200 μl/l air, QVOS102 had 6.4- and 2.9-fold higher LT50 values for lavender and ylang-ylang fumigation toxicity, respectively, than VOS48. Piperonyl butoxide, a potential inhibitor of cytochrome P450-dependent monooxygenase, increased fumigant toxicities of the two essential oils against QVOS102. The enhanced tolerance for the essential oil may have resulted from the enhancement of detoxifying enzymes associated with insecticide resistance. 相似文献
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介绍了采用模糊控制技术解决真空冻干生产线控制中大超调量、大滞后等问题的方法 ,详述了模糊控制系统的构成、主要功能和实现方法 相似文献
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在介绍PC键码特征的基础上,可利用AT89C2051来实现PC键盘的硬件设计.它具有结构简单、选择性强、便于实现等优点,特别适用于36个以下PC键盘的应用. 相似文献
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本文主要介绍了在DXDK800自动充填包装机中 ,采用一种新型的齿轮—蜗轮、蜗杆差速器来对膜片的进给速度进行微量的调整。及采用一种新型的可调式偏心链轮来调整横封辊的瞬时线速度 ,使其与料袋膜的进给速度相一致 相似文献
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CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing 总被引:2,自引:0,他引:2
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture. 相似文献