Design and implementation of an FPGA-based parallel graphics renderer for displaying CSG surfaces and volumes

In this paper, the design and implementation of a high-speed “CSG renderer” for displaying convex and concave objects and its performance analysis are presented. The renderer comprises a binary tree-structured depth generator that produces the depth values of a plane at each pixel on the display window simultaneously, and pipelined pixel processors that processes the depth values, a corner bender, and a frame-buffer.In this work, constructive solid geometry (CSG) scene models are used to simplify the hidden area removal and object interference testing. The field programmable gate array technology is used in the implementation.