八里庄钢筋混凝土桥控爆拆除

文中介绍在周期建筑，电力、电信等设计密集的环境中，爆破一座结构坚固的大型钢筋混凝土桥梁和桥台浆砌块石的爆破参数设计，局部部位技术处理措施以及孔内孔外延时相结合的非电起爆网路。     

Identification of delayed system using instrumental variable method

System identification uses system inputs and outputs to raise mathematical models.Various techniques of system identification exist that offer a nominal model and an uncertainty bound.Many practical systems such as thermal processes & chemical processes have inbuilt time delay.If the time delay used in the system model for controller design does not concur with the actual process time delay,a closed-loop system may be unstable or demonstrate unacceptable transient response characteristics so here the time delay is assumed to be time-invariant. This paper proposes on-line identification of delayed complex/uncertain systems using instrumental variable(Ⅳ) method.Parametric uncertainty has been considered which may be represented by variations of certain system parameters over some possible range.This method allows consistent estimation when the system parameters are associated with the noise terms,as the IV methods(IVM’s)usually make no assumption on the noise correlation configuration.The faster convergence of the parameters including noise terms has been proved in this paper.Iterative prefiltering(IP)method has also been used for the identification of the delayed uncertain system and the graphical results given in this paper demonstrate that the convergence results are inferior to the instrumental variable method.     

具有时变时滞耦合的二阶多主体系统的编队控制

多主体系统的编队控制是一类重要的网络协同控制问题.研究了在有向连接拓扑结构下,具有时变时滞耦合的二阶多主体系统的编队控制问题.通过一种多层领导机制的框架建模,得到了时不变编队、时变编队和时变轨迹追踪3种编队问题的充分性条件,并证明了各种预期队列是以指数的收敛速度形成的.数值仿真进一步验证了理论结果的正确性,为该理论在实际中应用起到指导作用.     

基于进化计算的兴趣建模

为实现对个体的兴趣建模,提出基于进化计算的建模(Evolutionary Computation Based Modeling,ECBM)方法。该方法采用定性和定量相结合的方式对个体的兴趣系统进行建模,首先通过定性分析构建个体的兴趣模型框架,然后通过进化计算(Evolutionary Computation)方法对模型参数自动进化。实验结果表明,ECBM能够通过数据驱动模式优化模型参数,并利用更新信息进化模型,使其不断逼近真实系统。     

A low power and small area all digital delay-locked loop based on ring oscillator architecture

A 133-500 MHz,5.2 mW @500 MHz,0.021 mm2 all digital delay-locked loop(ADDLL)is presented.The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator(ROSC)to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed.The proposed ADDLL has better immunity to PVT(process,voltage,and temperature)than most conventional DLLs,which do not update the control word signals after the locking process,since the control signals for slave delay line are updated in every 256 reference cycles.Fabricated in 0.13 um CMOS process,the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps.     

A note on circle packing

The problem of packing circles into a domain of prescribed topology is considered. The circles need not have equal radii. The Collins-Stephenson algorithm computes such a circle packing. This algorithm is parallelized in two different ways and its performance is reported for a triangular, planar domain test case. The implementation uses the highly parallel graphics processing unit (GPU) on commodity hardware. The speedups so achieved are discussed based on a number of experiments.     

基于IPv6组播的M-FHM IPv6切换技术

由于快速分层切换技术FHMIPv6将FMIPv6和HMIPv6切换技术结合起来,因此,在层次移动管理模型中部署快速切换时具有两种技术所具有的优点,可使切换延时进一步减少。文中通过对FHMIPv6的研究发现,其切换过程中DAD重复地址检测过程严重影响了切换性能,因此提出了基于IPv6组播的M-FHMIPv6切换技术。理论分析证明,M-FHMIPv6能有效减少DAD检测过程和各种信息交互的延迟。通过NS2实验仿真进一步说明:改进的M-FHMIPv6方案能减少切换延迟,平滑切换过程。