集群计算机上基于BSP模型的并行算法及其程序设计

文章分析了BSP模型和集群计算机的特点，给出了在集群计算机根据BSP模型设计并行算法及其软件的原则，举例说明了利用BSP模型代价公式定性分析并行算法性能的方法，并利用实验结果验证了得出的结论。结果表明模型的成功地抽象出了集群计算中影响算法性能的诸种因素，并通过代价公式反映出来，利用代价公式可以基本准确地估计并行算法代价，这对集群计算机上的并行算法及其软件及设计和优化具有重要的指导意义。     

指针推进移动性管理策略中指针链长度的概率

为了降低移动通信网络中位置跟踪操作的代价,指针推进策略被提出.显然,指针链长度的确定对这一策略的有效应用是至为重要的.已有论文假定移动台在位置区的逗留时间服从指数分布的条件下,对指针链的长度进行研究,但指数分布的特殊性,限制了其研究结果的应用.本文推广了上述结果,研究了移动台在位置区的逗留时间服从一般概率分布的指针推进策略,通过构造向量马氏过程,利用密度演化方法,导出了指针链长度的概率公式,这个公式可用于对各种指针推进策略性能的评价.     

A PROTOTYPE GRID FRAMEWORK FOR THE CHEMICAL PROCESS INDUSTRIES

This article presents a GRID framework for distributed computations in the chemical process industries. We advocate a generic agent-based GRID environment in which chemical processes can be represented, simulated, and optimized as a set of autonomous, collaborative software agents. The framework features numerous advantages in terms of scalability, software reuse, security, and distributed resource discovery and utilization. It is a novel example of how advanced distributed techniques and paradigms can be elegantly applied in the area of chemical engineering to support distributed computations and discovery functions in chemical process engineering. A prototype implementation of the proposed framework for chemical process design is presented to illustrate the concepts.     

Parallel path consistency

Filtering algorithms are well accepted as a means of speeding up the solution of the consistent labeling problem (CLP). Despite the fact that path consistency does a better job of filtering than arc consistency, AC is still the preferred technique because it has a much lower time complexity. We are implementing parallel path consistency algorithms on multiprocessors and comparing their performance to the best sequential and parallel arc consistency algorithms.^(1,2) (See also work by Kerethoet al. ⁽³⁾ and Kasif⁽⁴⁾) Preliminary work has shown linear performance increases for parallelized path consistency and also shown that in many cases performance is significantly better than the theoretical worst case. These two results lead us to believe that parallel path consistency may be a superior filtering technique. Finally, we have implemented path consistency as an outer product computation and have obtained good results (e.g., linear speedup on a 64K-node Connection Machine 2).     

A VLSI architecture for a half-edge-based corner detector

Corner detection is a low-level feature detection operator that is of great use in image processing applications, for example, optical flow and structure from motion by image correspondence. The detection of corners is a computationally intensive operation. Past implementations of corner detection techniques have been restricted to software. In this paper we propose an efficient very large-scale integration (VLSI) architecture for detection of corners in images. The corner detection technique is based on the half-edge concept and the first directional derivative of Gaussian. Apart from the location of the corner points, the algorithm also computes the corner orientation and the corner angle and outputs the edge map of the image. The symmetrical properties of the masks are utilized to reduce the number of convolutions effectively, from eight to two. Therefore, the number of multiplications required per pixel is reduced from 1800 to 392. Thus, the proposed architecture yields a speed-up factor of 4.6 over conventional convolution architectures. The architecture uses the principles of pipelining and parallelism and can be implemented in VLSI.     

A flexible architecture for distributed knowledge based systems with nomadic access through handheld devices

Nowadays any Knowledge Based System (KBS) realization needs of intercommunication among distributed components and to use non-connected and distributed data sources, which poses several challenges to the classical Artificial Intelligence field of KBS.

The multiagent paradigm and the use of ontologies are considered to be suitable tools to face the problems of designing and developing today KBS. On the other hand, using such networked KBS through handheld devices makes more efficient exploitation and interaction with the system.

This paper presents an open and flexible architecture for a distributed KBS and an application of it to construct a system for Psychological Disorders consulting, the so called PDA² (Psychological Disorder Assistant through PDA). We analyze the main features of the architecture as well as the agent tools we may use to construct it. Additionally, we present a support ontology for Psychological Disorders.     

Hardware system of the Earth Simulator

The Earth Simulator (ES), developed under the Japanese government’s initiative “Earth Simulator project”, is a highly parallel vector supercomputer system. In this paper, an overview of ES, its architectural features, hardware technology and the result of performance evaluation are described.

In May 2002, the ES was acknowledged to be the most powerful computer in the world: 35.86 teraflop/s for the LINPACK HPC benchmark and 26.58 teraflop/s for an atmospheric general circulation code (AFES). Such a remarkable performance may be attributed to the following three architectural features; vector processor, shared-memory and high-bandwidth non-blocking interconnection crossbar network.

The ES consists of 640 processor nodes (PN) and an interconnection network (IN), which are housed in 320 PN cabinets and 65 IN cabinets. The ES is installed in a specially designed building, 65 m long, 50 m wide and 17 m high. In order to accomplish this advanced system, many kinds of hardware technologies have been developed, such as a high-density and high-frequency LSI, a high-frequency signal transmission, a high-density packaging, and a high-efficiency cooling and power supply system with low noise so as to reduce whole volume of the ES and total power consumption.

For highly parallel processing, a special synchronization means connecting all nodes, Global Barrier Counter (GBC), has been introduced.     

计算机高速并行通信的实现方案

利用CPLD芯片实现单片机与ISA总线接口之间的高速并行通信，给出系统的总体设计方法及程序框图。采用这种通信方式，在12MHz晶振的MCS51单片机控制的数据采集系统中，可以满足与PCI04 ISA总线接口实时通信的要求，通信速率达200khit／s。在开发工具MAX plusⅡ下，完成了整个设计的输入、编译和仿真，达到了预期效果。本设计方案能够推广应用到计算机的高速并行通信中。     

多码CDMA系统中联合并行干扰抵消与迭代信道估计方法

本文针对多码CDMA系统提出了一种联合并行干扰抵消与迭代信道估计方法。该方法首先通过导频符号对信道进行估计，然后使用RAKE接收机后的软信息对信道参数进行修正，最后通过并行干扰抵消(PIC)去除多码干扰(MCI)。仿真结果表明，经过多次迭代后，该方法可显著地降低多码CDMA系统的误比特率平台。本文同时还给出了信道估计质量、码道数和PIC次数对多码CDMA系统性能的影响。