多位乘法器的多阶Booth算法的实现

讨论分析了传统Booth算法及改进二阶Booth算法的特点,提出一种适合多阶算法的一般通式及部分积的实现方法,可根据乘数的位宽采用不同的阶,一次扫描多位相邻的乘数位,由此最大限度地减少了部分积的数目,提高了乘法器的运算速度．     

反映的规律为本构关系的变分原理

为证明经典变分原理中存在反映的规律为本构关系的变分原理,从非线性弹性动力学的基本方程出发,应用变积方法建立非线性弹性动力学Hamilton原理.再应用对合变换法、Lagrange乘子法和局部代入法,将Hamilton原理变换为本构变分原理.论证了该变分原理反映的规律为本构关系,本研究以非线性材料为例,找到了一个新的材料本构关系的获得途径,为数值建模提供了理论依据.研究结果表明,补充和完善了经典变分原理中对3类基本规律的反映,即:最小势能原理反映的规律为平衡关系、最小余能原理反映的规律为连续关系和本构变分原理反映的规律为本构关系.     

乘法器复用技术在滑窗FIR滤波处理中的运用

随着超大规模集成电路的飞速发展,FPGA集成的硬件乘法器越来越多,内核时钟越来越快,使得FPGA在实时信号处理中得到广泛应用。介绍了FIR滤波运算的原理与硬件处理结构,通过乘法器的复用技术,解决了实现滑窗FIR滤波处理时,FPGA内部乘法器的高速运算与外部慢速数据率之间的矛盾。     

考虑可控负荷的多区域电力系统分布式模型预测负荷频率控制

由于同步发电机的惯性较大,导致传统的集中式负荷频率控制模式反应不够迅速,而用户侧具有快速响应能力的可控负荷资源为系统的频率调节提供了新机遇。研究了考虑用户侧可控负荷资源主动参与系统频率调节的多区域互联电力系统分布式模型预测负荷频率控制问题。通过建立的含可控负荷的多区域互联电力系统负荷频率响应模型及自动发电控制模型,基于连续时域交替方向乘子法和分布式模型预测控制方法,提出了一种用户侧可控负荷资源主动参与的多区域互联电力系统分布式模型预测最优负荷频率控制模型。基于修改的IEEE39节点三区域互联电力系统进行仿真验证,结果表明所提考虑可控负荷的分布式模型预测控制策略可显著减少系统恢复至稳态所需的时间。分布式控制策略的控制自由度更高,增强了系统的可控性。     

An Optimized Deep-Learning-Based Low Power Approximate Multiplier Design

Approximate computing is a popular field for low power consumption that is used in several applications like image processing, video processing, multimedia and data mining. This Approximate computing is majorly performed with an arithmetic circuit particular with a multiplier. The multiplier is the most essential element used for approximate computing where the power consumption is majorly based on its performance. There are several researchers are worked on the approximate multiplier for power reduction for a few decades, but the design of low power approximate multiplier is not so easy. This seems a bigger challenge for digital industries to design an approximate multiplier with low power and minimum error rate with higher accuracy. To overcome these issues, the digital circuits are applied to the Deep Learning (DL) approaches for higher accuracy. In recent times, DL is the method that is used for higher learning and prediction accuracy in several fields. Therefore, the Long Short-Term Memory (LSTM) is a popular time series DL method is used in this work for approximate computing. To provide an optimal solution, the LSTM is combined with a meta-heuristics Jellyfish search optimisation technique to design an input aware deep learning-based approximate multiplier (DLAM). In this work, the jelly optimised LSTM model is used to enhance the error metrics performance of the Approximate multiplier. The optimal hyperparameters of the LSTM model are identified by jelly search optimisation. This fine-tuning is used to obtain an optimal solution to perform an LSTM with higher accuracy. The proposed pre-trained LSTM model is used to generate approximate design libraries for the different truncation levels as a function of area, delay, power and error metrics. The experimental results on an 8-bit multiplier with an image processing application shows that the proposed approximate computing multiplier achieved a superior area and power reduction with very good results on error rates.     

Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam (UT) Sutra. This multiplier consists of bitwise multiplication and adder compressors. Compared with Vedic multipliers in the literature, the proposed design has a quantum cost of 111 with a reduction of 94% compared to the previous design. It has a garbage output of 30 with optimization of the best-compared design. Second, the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers. Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters. DesignI has separate binary two’s complement (B2C) and MUX circuits, while DesignII combines binary two’s complement and MUX circuits in one circuit. DesignI shows the lowest quantum cost, 231, regarding state-of-the-art. DesignII has a quantum cost of 199, reducing to 86.14% of DesignI. The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.     

Parallel crypto-devices for GF(p) elliptic curve multiplication resistant against side channel attacks

All elliptic curve cryptographic schemes are based on scalar multiplication of points, and hence its faster computation signifies faster operation. This paper proposes two different parallelization techniques to speedup the GF(p) elliptic curve multiplication in affine coordinates and the corresponding architectures. The proposed implementations are capable of resisting different side channel attacks based on time and power analysis. The 160, 192, 224 and 256 bits implementations of both the architectures have been synthesized and simulated for both FPGA and 0.13μ CMOS ASIC. The final designs have been prototyped on a Xilinx Virtex-4 xc4vlx200-12ff1513 FPGA board and performance analyzes carried out. The experimental result and performance comparison show better throughput of the proposed implementations as compared to existing reported architectures.     

矩形乘法器的另一结构设计

文章给出了矩形乘法器的另一个结构设计,该设计在计算速度上优于文献[1]的方案而劣于文献[2]的方案,在流水线分级方面则比文献[2]的方案有灵活性。这一实现把大整数乘的数据相关之时间代价降为1个二选一选通器加上3位加法器所需的时间,即把乘法器流水线的节拍时间值降到了该值,从而大大提高了用流水线实现大整数乘的效率。在某些应用中,用矩形乘法器来实现平行四边形乘法器的功能,则可大大降低规模。     

脉冲频率调制LLC串联谐振X光机电源

为了满足X光机电源输出电压调节范围宽的要求,提出了一种全桥LLC串联谐振高频高压电源,并利用仿真软件设计其控制电路,使设计方法更加简单.主电路采用全桥LLC串联谐振、高压变压器、单相双向对称倍压整流电路,从理论上分析系统的工作原理,并建立了LLC谐振变换器的基波等效模型,对主电路的参数进行了设计;在控制电路设计中,借助仿真软件得到补偿前系统近似的开环传递函数,再进行控制器的设计.仿真结果表明,输出电压可以在40~120 kV范围内连续可调,输出电压上升时间短、纹波小,在输出电压跳变过程中,动态调节时间很短,证明了所提出的拓扑和控制电路设计方法的正确性和可靠性.     

矩阵填充与主元分析在受损图像配准中的应用

本文提出了一种有效的针对受损图像(元素丢失)的图像配准方法。利用矩阵填充技术将受损图像的丢失元素恢复,然后将主元分析法(PCA)应用于尺度不变特征变换(SIFT)中进行图像的配准。针对SIFT算法采用128维特征向量表示特征点,存储空间、匹配时间与特征点数量成正比,文本采用主元分析法对多维特征向量进行降维处理,以提高运算效率;并采用高斯加权欧氏距离代替欧氏距离进行特征点的匹配。实验结果表明,该算法具有较好的稳定性、准确率和匹配速度,针对受损图像配准具有较好的鲁棒性,可应用在基于内容的图像与视频检索等机器视觉领域。