嵌入式虚拟仪器软件可重构设计技术研究

嵌入式虚拟仪器(EVI)软件可重构是指框架和功能的重构;结合面向对象技术和组件技术,系统地阐述了软件可重构模块化设计的原理、软件可重构算法、可重构软件结构框架设计和可重构软件开发方法;通过分析可重构软件的设计原理和设计思路,提出了一套比较详细的可重构软件的开发方法;经工程实践应用,设计方法合理可行,有效提高了嵌入式虚拟仪器软件的开发效率,达到软件复用及重构的目的。     

Xilinx FPGA的嵌入式系统开发过程

围绕Xilinx公司FPGA中的MicroBlaze软核微处理器,对其体系结构、设计流程和相关开发工具进行了详细介绍,并且通过一个实例说明了以MicroBlaze软核处理器为内核的嵌入式系统的开发过程。     

μC／OS—Ⅲ在Cortex—M3处理器上的移植

为了将μC／OS-Ⅲ移植到Cortex—M3处理器上,选用RealView MDK作为软件开发平台,针对Cortex—M3处理器特性编写了移植所需的C语言和汇编语言源代码,并验证了移植的正确性。移植后的μC／OS-Ⅲ能够稳定运行于Cortex～M3处理器上。该移植对大部分Cortex—M3处理器具有通用性,对其他架构处理器的μC／OS-Ⅲ移植具有参考作用。     

基于uIP与AJAX的动态Web服务器设计

针对远程信息监测系统中数据的实时采集更新问题,将AJAX和CGI应用到嵌入式Web服务器的设计中,实现了服务器与浏览器之间的动态信息交互。本文首先分析了uIP协议栈,并在协议栈之上设计了Web服务器,然后利用CGI服务程序处理来自客户端的XMLHttpRequest对象请求,实现动态Web功能。现场实验结果表明,嵌入式Web服务器降低了服务器端的资源开销,提高了响应速度。     

基于超声波的围岩松动圈实时监测系统设计

实时地掌握围岩松动圈的范围对矿藏的安全生产具有重要的意义。利用超声波探测的灵活性和准确性,本文提出了一种基于超声波的围岩松动圈监测系统设计方法。此方案利用超声波在岩体中的传播速度与岩体的受力状态和裂隙程度的关系来实时地监测围岩松动圈的情况,具有方便、灵活、易于操作等特点。     

LD3320的嵌入式语音识别系统的应用

语音交互系统是比较人性化的人机操作界面,它需要语音识别系统的支持。LD3320就是这样一款语音识别芯片。介绍了该芯片的工作原理及应用,给出了LD3320与微处理器的硬件接口电路及软件程序。随着高档MCU的不断出现,以MCU为核心的嵌入式语音交互系统会有非常好的应用前景。     

改进型时间触发嵌入式系统编程模式

对于成本敏感的嵌入式系统,通常因为资源有限而难以采用抢先式实时多任务操作系统。传统的基于超级循环的前后台编程方法和基于时间触发的合作式多任务编程方法对任务的划分需要较高的技巧。本文通过对基于时间触发合作式调度器的改进,建立了一种适用于小型嵌入式系统的通用编程模式,使这类系统的编程变得清晰、简单。     

Efficient design of SIW filters with knowledge‐embedded space mapping technique

This article presents an optimization technique for the design of substrate‐integrated waveguide (SIW) filters using knowledge‐embedded space mapping. An effective coarse model is proposed to represent the SIW filter. The proposed coarse model can be analyzed in the available commercial software ADS. The embedded knowledge includes not only formulas but also extracted design curves, which help to build the mapping between the coarse and fine models. The effectiveness of the proposed method is demonstrated through a design example of a six‐pole SIW filter. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2012.     

Run-time generation of partial FPGA configurations

This paper presents and evaluates a method of generating partial bitstreams at run-time for dynamic reconfiguration of sections of an FPGA. The method is intended for use in adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The proposed approach combines partial bitstreams of coarse-grained components to produce a new partial bitstream implementing a given circuit netlist. Topological sorting of the netlist is used to determine the initial positions of individual components, whose placement is then improved by simulated annealing. Connection routing is done by a breadth-first search of the reconfigurable area based on a simplified resource model of the reconfigurable fabric. The desired partial bitstream is constructed by merging together the default bitstream of the reconfigurable area, the relocated partial bitstreams of the components, and the configurations of the switch matrices used for routing. The approach is embodied in a code library that applications can use to create new bitstreams at run-time. For the members of a set of 29 benchmarks (both synthetic and application-derived) having between five and 41 components, the complete process of bitstream generation takes between 8 s and 35 s when running on an embedded PowerPC 405 microprocessor clocked at 300 MHz.     

Rapid software integration using structured methods

In this paper we discuss an approach to organizing the integration of 110,000 lines of C, SQL, Assembler, and microcode distributed over a network of 36 processors of four types so that it could be accomplished in six months. The software runs on a test system architecture consisting of a LAN-based workstation group and a set of VME-based embedded processors. By using structured methodology, parallelism in the integration process was achieved. The necessary stub tools were identified and developed before integration began. The principles followed and experiences of integrating the system are discussed.