The ΣΔ-BIST Method Applied to Analog Filters

This paper describes the -BIST method, defined as an analog BIST circuit in the context of mixed signal systems. The test procedure is based on the reuse of existing analog circuits configured as sigma-delta modulators in the analog domain. The test procedure reuses most of existing blocks in a mixed signal system, and thus has small area overhead. Test sensitivity is very high, detecting small component deviations. Moreover, the proposed test technique can be applied to continuous or sampled time circuits, and the test procedure can be developed in the field. The paper explains the method and presents practical results to validate the proposed approach.     

On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check

This paper proposes the Cross-Parity check as a method for an on-line detection of multiple bit-errors in registers or register files of microprocessors. Transient or soft errors caused by radiation as single event upsets (SEUs) or electromagnetic coupling are in the focus of this work. Especially for register files or register groups, an easy implementable error correction method is proposed, which can be implemented by software routines or additional hardware. The method is based on the logical interpretation of Cross-Parity vectors.     

Behavioral Testability Insertion for Datapath/Controller Circuits

A method for test synthesis in the behavioral domain is described.The approach is based on the notion of adding a test behavior to the normal-mode design behavior. This testbehavior describes the behavior of the design in test mode. Thenormal-mode design behavior and test-mode test behavior are combinedand then synthesized by any general-purpose synthesis system toproduce a testable design with inserted BIST structures. The testbehavior is derived from the design behavior using testabilityanalysis based on metrics that quantify the testability of signalsand variables embedded within behaviors. The insertion method iscombined with a behavioral test scheme thatintegrates a) the design controller and test controller, b) testingof the entire datapath and controller. Examples show that when thetestability insertion procedure is used to modify a behavior beforesynthesis, the resulting synthesized physical implementation isindeed more easily tested than an implementation synthesized directlyfrom the original behavior.     

SoC嵌入式flash存储器的内建自测试设计

深亚微米技术背景下，嵌入式存储器在片上系统芯片(system-on-a-chip，SoC)中占有越来越多的芯片面积．嵌入式存储器的测试正面临诸多新的挑战。本文论述了两种适合SoC芯片中嵌入式flash存储器的内建自测试设计方案。详细讨论了专用硬件方式内建自测试的设计及其实现，并且提出了一种新型的软硬协同方式的内建自测试设计。这种新型的测试方案目标在于结合专用硬件方式内建自测试方案并有效利用SoC芯片上现有的资源，以保证满足测试过程中的功耗限制，同时在测试时间和芯片面积占用及性能之间寻求平衡。最后对两种方案的优缺点进行了分析对比。     

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non-robust tests are under consideration. Experimental results given in this paper are based on a software generation of RSIC test sequences that can be easily generated in this case. For a built-in self-test (BIST) purpose, hardware generated RSIC sequences have to be used. This kind of generation will be shortly discussed at the end of the paper.     

基于MCU的可测试性设计

根据ＭＣＵ结构非常复杂且具有指令系统的特点,没有采用一般数字电路设计的从结构出发的ＤＦＴ技术,而是设定了ＭＣＵ的３种工作模式,提出了一种在ＭＣＵ中加入规模很小的模式选择电路,对部分电路作较小改动,就可以对芯片内的各块电路进行功能测试的方法。在完成了ＭＣＵ的可测性设计后进行了仿真,结果表明电路能正常工作在各种模式下。     

Low Cost BIST for Static and Dynamic Testing of ADCs

This paper presents a low cost test method for the static and dynamic characterization of analog-to-digital converters. The method is suitable for implementation in a SoC environment, as a built-in self test (BIST) solution. In the proposed approach, noise is used as the test signal. Theory of operation and practical results demonstrating the effectiveness of the method for INL, DNL, THD and SINAD characterization are presented. The BIST surface overhead caused by the noise generator is only 7.4% of the ADC total area. The reduced number of data samples required allows a reduction of about 7.5× in test time, in comparison to the histogram method.Maria da Gloria Cataldi Flores was born in Santa Maria, Brazil, in 1978. She received the electrical engineering degree in 2000 from Universidade Federal de Santa Maria (UFSM) and the M.S. degree engineering in 2003 from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then, she has been working as a design engineer in an EAS Supply brazilian company. Her main research interests include mixed-signal and analog testing and digital signal processing.Marcelo Negreiros was born in Porto Alegre, Brazil, in 1969. He received the electrical engineering degree in 1992 and the M.S. degree engineering in 1994, both from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then he was been working as an associate researcher in the Signal Processing Lab. (LaPSI) of the Electrical Engineering Department at UFRGS. Since 2000 he also works toward a Ph.D. in Computer Science from UFRGS. His main research interests include mixed-signal and analog testing and digital signal processing.Luigi Carro was born in Porto Alegre, Brazil, in 1962. He received the Electrical Engineering and the M.Sc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In 1996 he received the Ph.D. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design and Digital Signal processing disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in Embedded Systems, Digital Signal Processing, and VLSI Design. His primary research interests include mixed-signal design, digital signal processing, mixed-signal and analog testing, and fast system prototyping. He has published more than 90 technical papers in those topics and is the author of the book Digital Systems Design and Prototyping (in portuguese).Altamiro A Susin was born in Vacaria-RS, Brazil, in 1945. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1972 and 1977, respectively. Since 1968 he worked in the start up of Computer Centers of two local Universities. In 1981 he got his Dr. Eng degree from Institut National Polytechnique de Grenoble-France. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible by courses in VLSI Architecture and is also thesis director. His main research interests are Integrated Circuit Architecture, Embedded Systems, Signal Processing with more than 50 technical papers published in those domains. He is/was responsible for several R&D projects either funded with public and/or industry resources.Felipe Ricardo Clayton received the B.S. degree in Electrical Engineering from State University of Campinas (UNICAMP), Brazil, in 1986. He worked at CPqD (Brazilian PTT R&D Center) till 1996 designing analog and mixed signal circuits for telecom and automotive applications. From 1997 to the second half of 1998, he worked at Instituto Superior Técnico (IST), Lisbon, Portugal, under the guidance of Prof. Carlos Azeredo Leme on development of CMOS RF circuits. Since October 1998 he had worked for Motorola SPS. Now he is head of the Power Managment Group at Freescale.Cristiano Benevento received his B.S. degree in Electrical Engineering from Universidade Estadual de Campinas (Unicamp), Brazil, in 1997. He worked at Motorola Cellular Infrastructure Group until August 2000 as a Systems Engineer. He joined Motorola Semiconductor Product Sector in August 2000 as IC Designer for Power Management Group and is now at Freescale.     

Simultaneous Static Testing of A/D and D/A Converters Using a Built‐in Structure

Static testing of analog‐to‐digital (A/D) and digital‐to‐analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built‐in self‐test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations.     

实用模拟BIST的基本原则

实用模拟BIST有潜力降低IC测试成本,以及产品上市时间。20多年来,研究人员和半导体制造商一直在试图开发一种针对混合信号IC的实用模拟BIST(内置自检)。这种技术能够用数字测试仪作混合信号IC测试,以及简化的多址测试,从而能减少IC测试成本,以及IC上市时间。其它预期优点还有更快的测试开发,以及系统上的自检等。     

Combining Scan Test and Built-in Self Test

For digital chips containing functional logic and embedded memories, these are usually tested separately: Scan test is used for testing functional logic; Memory Built-in Self Test (MBIST) is run for embedded memories. A new approach is proposed to exercise scan test and MBIST in parallel in order to reduce production test time and improve stress tests. It requires only small additional logic and allows to simultaneously run both test modes. In general, the approach can be used to control simultaneously scan test and any Built-in Self Test (BIST) providing a simple pass/fail result.