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针对FPGA的逻辑资源测试,提出了一种内建自测试方法.测试中逻辑资源划分为不同功能器件,对应各个功能器件设计了相应的BIST测试模板.在此基础上进一步利用FPGA的部分重配置性能优化BIST测试过程,最终在统一的BIST测试框架下,采用相对较少的配置次数完成了逻辑资源固定故障的全覆盖测试. 相似文献
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文中提出了一种利用处理器的指令系统编写特定程序,通过程序运行来控制完成整个存储器内建自测试过程的方法.基于此方法的设计已经成功应用于一款处理器中,有效地提高了芯片的可测试性和应用系统的容错性. 相似文献
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Steve Sunter 《电子设计技术》2011,18(2):35-38
实用模拟BIST有潜力降低IC测试成本,以及产品上市时间。20多年来,研究人员和半导体制造商一直在试图开发一种针对混合信号IC的实用模拟BIST(内置自检)。这种技术能够用数字测试仪作混合信号IC测试,以及简化的多址测试,从而能减少IC测试成本,以及IC上市时间。其它预期优点还有更快的测试开发,以及系统上的自检等。 相似文献
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In this article we propose a multiple-output parity bit signature generation method for exhaustive testing of VLSI circuits. Given a multiple-output combinational circuit, a parity bit signature is generated by first EXORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator. The method preserves all the desirable properties of the conventional single-output circuits response analyzers and can be readily implemented using the current VLSI technology. 相似文献
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Eduardo J. Peralías Adoración Rueda José L. Huertas 《Journal of Electronic Testing》2001,17(5):373-383
Two alternative BIST schemes are proposed for structural testing of pipelined Analog-to-Digital Converters (ADC). They are oriented to fault detection in the converter stages rather than to measure the whole ADC electrical performance parameters. The operational principle of both strategies relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a simple DC stimuli set which is easily obtained, without strong precision requirements, by a resistive network. The main differences between both strategies relate to the way the output response is evaluated. In the BIST#1 scheme, analog and digital outputs are compared with reference levels generated with a reference D/A converter and a counter. In the BIST#2 strategy, only digital outputs are available and they are compared with fault-free values previously stored in an on-chip register. The new techniques are intended to be used in pipelined converters of an arbitrary number of conversion stages and with a digital self-correction mechanism. 相似文献
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M.H. Tehranipour S.M. Fakhraie Z. Navabi M.R. Movahedin 《Journal of Electronic Testing》2004,20(2):155-168
We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modify the controller to interpret some of the instructions differently only within the initial test mode. In this paper, we have proposed a fuctional self-test methodology that is deterministic in nature. In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests. We first start with testing processor core using our proposed architedture. Once the testing of the processor core is completed, this core is used to test the embedded SRAMs. A test algorithm which utilizes a mixture of existing memory testing techniques and covers all important memory faults is presented in this paper. The proposed memory test algorithm covers 100% of the faults under the fault model plus a data retention test. The hardware overhead in the proposed architecture is shown to be negligible. This architecture is implemented on UTS-DSP (University of Tehran and Iran Communicaton Industries (SAMA)) IC which has been designed in VLSI Circuits and Systems Laboratory. 相似文献
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重新播种的测试方法是一种内建自测试方法,它可以用来提高伪随机测试矢量的故障覆盖率。介绍了 三种重新播种的测试方法,它们分别是使用很少种子的内建自测试重新播种方法、多重多项式线性反馈移位寄存器 的重新播种方法和使用部分线性反馈移位寄存器的重新播种方法。这三种方法在测试的硬件开销方面或在编码效率 等方面有所改进。 相似文献
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This paper presents a low‐cost RF parameter estimation technique using a new RF built‐in self‐test (BIST) circuit and efficient DC measurement for 4.5 to 5.5 GHz low noise amplifiers (LNAs). The BIST circuit measures gain, noise figure, input impedance, and input return loss for an LNA. The BIST circuit is designed using 0.18 μm SiGe technology. The test technique utilizes input impedance matching and output DC voltage measurements. The technique is simple and inexpensive. 相似文献