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排序方式: 共有41条查询结果,搜索用时 15 毫秒
1.
随着器件沟道尺寸的不断缩小,短沟道效应(SCE)和漏致势垒降低效应(DIBL)对常规类MOSFET结构的石墨烯纳米条带场效应管(GNRFET)影响变大,从而引起器件性能下降。文中提出了一种新型采用非对称HALO-LDD掺杂结构的GNRFET,其能够有效抑制器件中SCE和DIBL,改善器件性能。并采用一种量子力学模型研究GNRFET的电学特性,该模型基于二维NEGF(非平衡格林函数)方程和Poisson方程自洽全量子数值解。结合器件的工作原理,研究了GNRFET的电学特性和器件结构尺寸效应,通过与采用其他掺杂结构的GNRFET的电学特性对比分析,发现这种掺杂结构的石墨烯纳米条带场效应管具有更低的泄漏电流、更低的亚阈值斜率和DIBL以  相似文献   
2.
    
The major purpose of this paper is to find an alternative configuration that not only minimizes the limitations of single-gate (SG) MOSFETs but also provides the better replacement for future technology. In this paper, the electrical characteristics of SiGe double-gate N-MOSFET are demonstrated and compared with electrical characteristics of Si double-gate N-MOSFET. Furthermore, in this paper the electrical characteristics of Si double-gate N-MOSFET are demonstrated and compared with electrical characteristics of Si single-gate N-MOSFET. The simulations are carried out for the device at different operational voltages using Cogenda Visual TCAD tool. Moreover, we have designed its structure and studied both Id-Vg characteristics for different voltages namely 0.05, 0.1, 0.5, 0.8, 1 and 1.5 V and Id-Vd characteristics for different voltages namely 0.1, 0.5, 1 and 1.5 V at work functions 4.5, 4.6 and 4.8 eV for this structure. The performance parameters investigated in this paper are threshold voltage, DIBL, subthreshold slope, GIDL, volume inversion and MMCR.  相似文献   
3.
    
An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted Id-Vds, Id-Vgs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.  相似文献   
4.
    
This paper considers the depletion regions at the source and drain sides in a symmetric junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with trapped charges working in subthreshold condition. The effects of depletion layers on the potential, threshold voltage, drain‐induced barrier lowering (DIBL), and the current of the device have been investigated. The channel of the transistor is divided into 4 regions: 2 regions without and with trapped charges and 2 depletion regions on either side of the channel. Solving the 2‐dimensional Poisson's equation, a semianalytical model for the potential is achieved in these regions and the threshold voltage, the DIBL, and the current are calculated. Also, the depletion widths are calculated during the modeling and their variation against the positive and negative trapped charges is investigated. To show the importance of the depletion layers, another junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor without depletion layers is considered and the mentioned electrical properties of the 2 devices are compared with each other. Smaller central potential, threshold voltage, and current and higher DIBL are achieved when the depletion layers are considered. Good agreement between the results of the proposed model and the simulated results by TCAD software shows the physical validity of the proposed model.  相似文献   
5.
    
In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behaviour of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.  相似文献   
6.
An analytical surface potential model for the single material double work function gate(SMDWG) MOSFET is developed based on the exact resultant solution of the two-dimensional Poisson equation. The model includes the effects of drain biases, gate oxide thickness, different combinations of S-gate and D-gate length and values of substrate doping concentration. More attention has been paid to seeking to explain the attributes of the SMDWG MOSFET, such as suppressing drain-induced barrier lowering(DIBL), accelerating carrier drift velocity and device speed. The model is verified by comparison to the simulated results using the device simulator MEDICI. The accuracy of the results obtained using our analytical model is verified using numerical simulations. The model not only offers the physical insight into device physics but also provides the basic designing guideline for the device.  相似文献   
7.
从自洽求解二维泊松方程和薛定谔方程出发,编制出计算GaN HFET内不同栅、漏电压下沟道能带、电子气密度及量子电容的软件,研究场效应管的电荷控制和DIBL。在异质结沟道阱研究中,改变栅电压算出的电子气密度及量子电容同C-V实验测试结果相吻合,证明求解薛定谔方程是研究异质结场效应管电荷控制的有效方法。考虑外沟道渗透到内沟道的电场梯度以后,算出了场效应管的电子气密度及量子电容。场效应管模拟算得的量子电容同实验测得的栅-源和栅-漏电容相吻合。研究了不同栅、漏电压和电场梯度渗透下的内沟道能带,发现漏电压引起的电场梯度渗透使内沟道能带下弯,导致阈值电压负移。证明阈值电压负移由外沟道渗透到内沟道的电场梯度产生,用自洽能带计算方法可算得漏电压引起的阈值电压负移。提出使用能带剪裁优化设计异质结构来抑制DIBL的新理念。同有限元变分软件的类MESFET模拟相比,新能带计算软件可以求得电荷控制中的量子行为。由此提出编制异质结场效应管模拟软件的设想。  相似文献   
8.
This paper proposes an electrical method of extracting mechanical stress in n-MOSFETs and analyzes the influence of dummy active patterns on mechanical stress induced by spin-on-glass-filled shallow trench isolation (SOG-filled STI). The proposed method requires only the maximum transconductance gm,max and measured subthreshold current Id(sub.), eliminating the effect of deviations of the mobility μ and effective channel length Leff that occurred in a previous method using μ. In addition, it eliminates the measurement error due to the drain induced barrier lowering (DIBL) effect in a previous method using Id(sub.). The tensile stress σt in the experimental n-MOSFETs was measured as several hundred mega Pascals. An increase of separation distance d between dummy active regions and the Si active region resulted in a decrease of σt for d > 0.2 μm. But, σt decreased when d decreased from 0.2 to 0.09 μm.  相似文献   
9.
In this paper, a novel design of the double doping polysilicon gate MOSFET device is proposed, which has a p+ buried layer near the drain, and relatively thicker D-gate oxide film (DDPGPD MOSFET). The detailed fabrication process for this device is designed using process simulation software called TSUPREM, and the device structure plan is further used in MEDICI simulation. The effect of gate doping concentration is investigated, and it is found that the device Vth is only influenced by the S-gate; furthermore, the device can get a larger driving current by increasing the doping concentration of D-gate. Compared to other conventional DDPG MOSFETs, the short-channel effects (SCEs) including the off-state current, the gate leakage current and the drain induced barrier lowering effect (DIBL) can be effectively suppressed by the p+ buried layer and thicker D-gate oxide film. Additionally, the other parameters of the device such as the driving current are not seriously affected by the proposed design modifications.  相似文献   
10.
随着集成电路产业的迅速发展,CMOS工艺已进入≥22nm特征尺寸的研究。讨论了Halo结构在当前工艺尺寸等比例缩小挑战背景下的应用情况。与传统长沟器件结构进行了比较,指出由于短沟效应(SCE)和漏致势垒降低(DIBL)效应需要专门工艺来克服,Halo注入通过在沟道两侧形成高掺杂浓度区,达到对SCE和DIBL进行有效抑制的目的,现已成为备受关注的结构。针对有关Halo的研究内容进行综述,并对其在CMOS工艺等比例缩小进程中所起的作用进行评述,对Halo的发展趋势进行了展望。  相似文献   
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