Hybrid DPWM implementation using coarse and fine programmable ADLL

In the paper we propose a novel architecture and implementation of 11-bit Digital Pulse Width Modulator (DPWM) circuit based on previously known building blocks. Linearized Class-AD Double-sided (LADD) algorithm has been used to calculate the DPWM signals of the 11-bit resolution hybrid DPWM for a Class-AD digital audio amplifier. Noise-shaping process is used to support high fidelity with practical values of time resolution. The proposed DPWM circuit is composed of 8-bit counter and Analog Delay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fine programmable delay element is used to adjust the delay time of delay line and lock it to required time. The coarse- as well as fine-delay lines are implemented as a cascade of variable-delay elements based on shunt capacitor delay element or single-ended Schmitt trigger. The proposed 11-bit DPWM circuit, at a switching frequency of 352.8 kHz and clock generator frequency of 90.3 MHz allows us to attain SNR of 120 dB and THD of the output signal less than 0.1% within the audio baseband and modulation index M=0.95. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) for real CMOS process are presented.     

基于二分校准的混合型数字脉宽调制器

提出了一种基于混合型数字脉宽调制器(HDPWM)的带延迟线二分法校准机制的新电路结构,能有效地提高DPWM的线性度。详细介绍了混合型DPWM的工作原理,阐述了基于二分法机制的自校准电路的整体结构。分析了该结构的后仿真结果,并与带延迟锁相环(DLL)结构的DPWM的后仿真结果相比较。在32 MHz的时钟下,该电路成功实现了开关频率为2 MHz的数字DC-DC变换器中的9-bit DPWM。该电路基于0.13μm 1.2V CMOS工艺实现,最大差分非线性(DNL)仅为0.136 LSB,积分非线性(INL)为0.15 LSB。     

基于双脉宽调制方式的谐波抑制技术

针对谐波的产生会导致一些用电设备,特别是精密仪器出现工作故障、甚至损坏,提出了一种双脉宽调制方式,可以有效地抑制输出电流特定次谐波.分析了双脉宽调制方式的基本原理,给出了控制信号频谱的仿真比较结果,并对仿真与实验的数据分析,验证了该调制方式可以对直流电源的输出电流特定次谐波进行抑制.     

一种用于数字峰值电流模Buck的高精度DPWM设计

为减小脉冲关断延迟,提出了一种用于数字峰值电流模Buck的高精度数字脉冲宽度调制器(DPWM)的设计方案。采用粗调与细调相结合的分段式架构思想,粗调部分由全局时钟控制计数器-比较器模块构成,细调部分由锁相环组成的相移电路、计数器-比较器、多路选择器和逻辑门构成,以此产生不同精度的两段式延迟叠加,实现较高的DPWM输出精度。采用Vivado和Xilinx7系列FPGA,仿真并测试了搭载高精度DPWM的Buck。仿真结果表明,DPWM时间分辨率为250 ps,精度为0.01%。此外,测试结果表明,与低精度DPWM相比,设计的高精度DPWM一定程度上抑制了系统的极限环振荡,提高了Buck的环路带宽及系统稳定性。     

基于I-DPWM的三电平中点钳位光伏逆变器漏电流抑制方法

对于三电平中点钳位光伏逆变器,基于断续脉宽调制(discontinuous pulse width modulation, DPWM)并通过选择特定矢量进行钳位控制的方法,存在矢量分解计算时间长、注入共模电压分量和漏电流过大等不足。对此,提出了一种基于I-DPWM的三电平中点钳位光伏逆变器漏电流抑制方法。通过计算各类DPWM等效调制波来解析注入的低频共模电压分量。针对低频共模电压分量最小的DPWM1,在低频共模电压不连续点注入新的零序分量,通过减小低频共模电压来抑制漏电流幅值。同时,采用载波实现DPWM,免去了复杂的矢量运算。最后,在Matlab/Simulink平台建立了20 kW三电平中点钳位光伏逆变器的仿真模型,同时结合所设计的125 W实验样机验证了所提方法的有效性。     

基于载波调制的三电平并网逆变器断续调制策略

首先介绍了三电平逆变器断续调制法的原理及产生方法,对连续脉宽调制PWM方法和断续PWM(DPWM)调制法的性能进行了对比分析。然后提出了一种基于载波调制的优化方案,可以使断续调制法与非单位功率因数运行条件相适应,且采用该优化DPWM调制法的三电平逆变器在非单位功率因数条件下运行时可以获得更小的开关损耗。仿真和实验结果均验证了该方法的正确性与可行性。     

Phase-shifted Discontinuous Pulse-Width Modulation Methods for Multi-level Inverters Operated in Over-modulation Range

This article presents combinations of the generic phase-shifted pulse-width modulation method with conventional discontinuous pulse-width modulation methods operated in the over-modulation range. The treated discontinuous methods are the third harmonic injection, Depenbrock's DPWM1, and Ogasawara's DPWM2. The significant advantage of the present approach over the conventional phase disposition pulse-width modulation method is the equal power flow between the H-bridges and the improved distribution of the switching operations number between them. Furthermore, they provide improved linearity in the over-modulation range. The proposed pulse-width modulation methods are analyzed by extensive simulation results. Several aspects, such as the total harmonic distortion factor of the inverter output currents and voltages, harmonic content, frequency spectrum distribution, and switchings number, are studied.     

A digitally controlled PWM/PSM dual-mode DC/DC converter

A digitally controlled pulse width modulation/pulse skip modulation(PWM/PSM) dual-mode buck DC/DC converter is proposed.Its operation mode can be automatically chosen as continuous conduction mode (CCM) or discontinuous conduction mode(DCM).The converter works in PSM at DCM and in 2 MHz PWM at CCM.Switching loss is reduced at a light load by skipping cycles.Thus high conversion efficiency is realized in a wide load current.The implementations of PWM control blocks,such as the ADC,the digital pulse width modulator(DPWM) and the loop compensator,and PSM control blocks are described in detail.The parameters of the loop compensator can be programmed for different external component values and switching frequencies, which is much more flexible than its analog rivals.The chip is manufactured in 0.13μm CMOS technology and the chip area is 1.21 mm~2.Experimental results show that the conversion efficiency is high,being 90%at 200 mA and 67%at 20 mA.Meanwhile,the measured load step response shows that the proposed dual-mode converter has good stability.     

基于MMC的STATCOM直流侧电压均衡控制的研究

由于MMC特殊的拓扑结构,基于MMC的STATCOM有很多的优点,但这种拓扑也使得电容电压平衡控制成为难点。针对MMC STATCOM直流侧电容电压不平衡问题,通过分析MMC STATCOM的数学模型,基于解耦变换将有功和无功解耦分离,提出通过系统直流电压控制和基于排序的均压控制来平衡其直流侧电容电压的策略。系统直流电压控制用来确定电容电压稳定基准值和有功功率的交换,基于排序的均压策略用来平衡每个桥臂上所有子模块的电容电压。通过Matlab/Simulink仿真表明,该方法可以有效地稳定STATCOM直流侧电压。     

高精度数字PWM在DC/DC变换器中的应用

提出了一种采用现场可编程门阵列(Field Programmable Gate Arrays,FPGA)产生高精度DPWM(Digital Pulse Width Module)驱动信号控制BUCK变换器的数字控制方案.介绍了数字PWM控制器各部分的功能以及具体实现.以5V输入、1.3V输出的同步整流BUCK电路为主电路,实现了全数字、高精度、高频率的DC/DC控制器.