Design and experimental investigation of the high efficiency 1.5 W/4.2 K pneumatic-drive G-M cryocooler

The development of a high cooling power and high efficiency 4.2 K two stage G-M cryocooler is critically important given its broad applications in low temperature superconductors, MRI, infrared detector and cryogenic electronics. A high efficiency 1.5 W/4.2 K pneumatic-drive G-M cryocooler has recently been designed and developed by ARS. The effect of expansion volume rate and operation conditions on the cooling performance has been experimentally investigated. A typical cooling performance of 1.5 W/4.2 K has been achieved, and the minimum temperature of the second stage is 2.46 K. The steady input power of the compressor at 60 Hz is 6.8 kW, while the operation speed of the rotary valve is 30 rpm. A maximum cooling power of 1.75 W/4.2 K has been obtained in test runs.     

Effect of strain rate on the dynamic compressive mechanical behaviors of rock material subjected to high temperatures

Strain rate is not only an important measure to characterize the deformation property, but also an important parameter to analyze the dynamic mechanical properties of rock materials. In this paper, by using the SHPB test system improved with high temperature device, the dynamic compressive tests of sandstone at seven temperatures in the range of room temperature to 1000 °C and five impact velocities in the range of 11.0–15.0 m/s were conducted. Investigations were carried out on the influences of strain rate on dynamic compressive mechanical behaviors of sandstone. The results of the study indicate that the enhancement effects of strain rates on dynamic compressive strength, peak strain, energy absorption ratio of sandstone under high temperatures still exist. However, the increase ratios of dynamic compressive strength, peak strain, and energy absorption ratio of rock under high temperature compared to room temperature have no obvious strain rate effects. The temperatures at which the strain rates affect dynamic compressive strength and peak strain most, are 800, and 1000 °C, respectively. The temperatures at which the strain rates affect dynamic compressive strength and peak strain weakest, are 1000 °C, and room temperature, respectively. At 200 and 800 °C, the strain rate effect on energy absorption ratio are most significant, while at 1000 °C, it is weakest. There are no obvious strain rate effects on elastic modulus and increase ratio of elastic modulus under high temperatures. According to test results, the relationship formula of strain rate with high temperature and impact load was derived by internalizing fitting parameters. Compared with the strain rate effect at room temperature condition, essential differences have occurred in the strain rate effect of rock material under the influence of high temperature.     

Modeling the effect of deep traps on the capacitance–voltage characteristics of p-type Si-doped GaAs Schottky diodes grown on high index GaAs substrates

Numerical simulation, using SILVACO-TCAD, is carried out to explain experimentally observed effects of different types of deep levels on the capacitance–voltage characteristics of p-type Si-doped GaAs Schottky diodes grown on high index GaAs substrates. Two diodes were grown on (311)A and (211)A oriented GaAs substrates using Molecular Beam Epitaxy (MBE). Although, deep levels were observed in both structures, the measured capacitance–voltage characteristics show a negative differential capacitance (NDC) for the (311)A diodes, while the (211)A devices display a usual behaviour. The NDC is related to the nature and spatial distribution of the deep levels, which are characterized by the Deep Level Transient Spectroscopy (DLTS) technique. In the (311)A structure only majority deep levels (hole traps) were observed while both majority and minority deep levels were present in the (211)A diodes. The simulation, which calculates the capacitance–voltage characteristics in the absence and presence of different types of deep levels, agrees well with the experimentally observed behaviour.     

Enhance cycling performance of LiMn2O4 cathode by Sr2+ and Cr3+ doping

Spinel LiSr_0·1Cr_0·1Mn_1·8O₄ was synthesised by high temperature solid state method in order to enhance the electrochemical performance. The LiSr_0·1Cr_0·1Mn_1·8O₄ (LSCMO) materials were characterised by X-ray diffraction (XRD), scanning electron microscopy (SEM) and electrochemical tests. The XRD and SEM studies confirm that LSCMO had spinel crystal structure with a space group of Fd3m, and the particle of LSCMO shows irregular shape. The cyclic voltammetry data illustrated that the heavy current charge–discharge performance of LMO was improved by Sr²⁺ and Cr³⁺ doping. The galvanostatic charge–discharge of LSCMO cathode materials was measured at 1, 5, 10 and 20 C. The results indicated that LSCMO improved the capacity retention.     

采用信息增益率的混合入侵检测模型设计

针对现有混合入侵检测模型仅定性选取特征而导致检测精度较低的问题，同时为了充分结合误用检测模型和异常检测模型的优势，提出一种采用信息增益率的混合入侵检测模型.首先，利用信息增益率定量地选择特征子集，最大程度地保留样本信息；其次，采用余弦时变粒子群算法确定支持向量机参数构建误用检测模型，使其更好地平衡粒子在全局和局部的搜索能力，然后，选取灰狼算法确定单类支持向量机参数构建异常检测模型，以此来提高对最优参数的搜索效率和精细程度，综合提高混合入侵检测模型对攻击的检测效果；最后，通过两种数据集进行仿真实验，验证了所提混合入侵检测模型具有较好的检测性能.     

基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

Influence of Bridgman solidification on microstructures and magnetic behaviors of a non-equiatomic FeCoNiAlSi high-entropy alloy

The non-equiatomic FeCoNiAlSi alloy is prepared by the Bridgman solidification (BS) technique at different withdrawal velocities (V = 30, 100, and 200 μm/s). Various characterization techniques have been used to study the microstructure and crystal orientation. The morphological evolutions accompanying the crystal growth of the alloy prepared at different withdrawal velocities are nearly the same, from equiaxed grains to columnar crystals. The transition of coercivity is closely related to the local microstructure, while the saturation magnetization changes little at different sites. The coercivity can be significantly reduced from the equiaxed grain area to the columnar crystal area when the applied magnetic field direction is parallel to the crystal growth direction, no matter what is the withdrawal velocity. In addition, the alloy possesses magnetic anisotropy when the applied magnetic field is in different directions.     

高可用性DHCP服务的设计与实现

分析了建立高可用性DHCP服务的迫切需求,根据DHCP服务体系结构,提出了DHCP服务的设计方法,并进行了周密的系统设计和系统部署,总结出了大型局域网部署DHCP服务的优化策略。     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.