高频数字锁相环的研究

论文阐述了１００ＭＨｚ数字锁相环的设计过程，用１０ＭＨｚ晶体振荡器对１００ＭＨｚ数字压控振荡器进行锁相，使１００ＭＨｚ输出信号指标得到很大改善。论文还分析了各单元电路，关键点时域波形测试，频谱测试。     

A sensorless brushless dc motor system

This paper describes a brushless dc motor system without position or speed sensor. The brushless motor consists of a permanent magnet synchronous motor and a voltage-source inverter capable of controlling the amplitude and frequency of voltage. The rectangular-shaped stator current with a conducting interval of 120° (electrical) is controlled to be in phase with the trapezoidal back electromotive force. This results in producing maximum torque. Variable speed is achieved by adjusting the average motor voltage similarly to chopper control of dc motors. In this paper, two sensorless position detecting methods, i.e., an “indirect method” suited for the lower-speed range and a “direct method” suited for the higher-speed range are proposed. The combination of the two makes it possible to detect the rotor position over a wide-speed range. Furthermore, a speed-sen-sorless PLL control is proposed in applying the principle of the direct method. Experimental results obtained from a prototype brushless dc motor are shown to confirm the validity of the sensorless drive. The starting procedure of the motor also is discussed because it is impossible to detect the rotor position at a standstill.     

数字频率合成技术在地球站中的应用

数字分频式微波频率合成器,具有结构简单,造价低,良好的低相嗓特性等优点,因而被通信卫星地球站所广泛采用。论述了数字分频式频率合成技术在工星通信地球站中的应用,提出了采用高度集成锁相环器件:PE3336设计一种低相噪特性的微波数字频率源的工程实例,并将之用于某通信卫星转发器地球站设备中。     

A low power and small area all digital delay-locked loop based on ring oscillator architecture

A 133-500 MHz,5.2 mW @500 MHz,0.021 mm2 all digital delay-locked loop(ADDLL)is presented.The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator(ROSC)to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed.The proposed ADDLL has better immunity to PVT(process,voltage,and temperature)than most conventional DLLs,which do not update the control word signals after the locking process,since the control signals for slave delay line are updated in every 256 reference cycles.Fabricated in 0.13 um CMOS process,the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps.     

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22 GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6 dBc/Hz at 1 MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1 mW. The chip with an area of 1.048 × 1.076 mm² is fabricated in a TSMC 0.18 μm CMOS 1P6M technology process.     

A novel clock generation algorithm for system-on-chip based on least common multiple

Due to increase in the number of Intellectual Property (IP) cores, clock generation in current day System-on-Chips (SoCs) is facing a crisis. The conventional method of using a dedicated Phase Locked Loop (PLL) to generate the clock for each IP core is becoming inefficient in terms of power and cost. We propose an algorithm based on Least Common Multiple (LCM) to minimize the number of PLLs required to generate the clocks for the IP cores in a SoC. This is done by finding an Optimum Operating Frequency (OOF) for each IP core within 10% below the maximum operating frequency of the core. The OOF is chosen such that the LCM of the OOF of all the IP cores is minimized. Simulated annealing is used to find the LCM. This LCM is the crucial high frequency from which maximum number of clocks can be derived by clock dividers.     

甚高频信号源的设计

为了给小型信标模拟器提供甚高频载波,利用锁相环（phase loop lock,PLL）频率合成原理,使用集成锁相频率合成器ADF4360-8设计甚高频（ultra high frequency,UHF）信号源,详述了电路的硬件设计,简要介绍了软件设计。实验结果表明,频率误差小于±0.002%,达到了预期的技术指标。     

基于SMO的PMSM磁极位置检测技术

为构造低成本、高可靠性的永磁同步电机(PMSM)无位置传感器控制系统,对基于滑模观测器(SMO)的PMSM磁极位置检测技术进行研究.基于滑模变结构和矢量控制理论设计了滑模观测器,用于估算电机的反电势,并构造了采用锁相环(PLL)结构的磁极位置检测单元.仿真和实验结果表明,所设计的观测器能较准确地估算电机反电势,但存在一定的高频抖振,而锁相环单元能在很大程度上减小高频分量对角度估算的影响,提出的方法能实现较高精度的磁极位置检测.     

同步旋转坐标系下的BLDCM滑模观测器算法设计

为了实现无位置传感器无刷直流电机(BLDCM)矢量控制系统中电机转子位置的准确估计,提出了一种基于同步旋转坐标系的滑模观测器算法。该方法直接在同步旋转坐标系中设计滑模观测器,以获取电机反电动势信息,再通过锁相环技术从估计的反电动势中提取电机转子的速度和位置角度信息。针对滑模观测器的高频抖振问题,采用饱和函数代替滑模观测器的符号函数。最后,通过仿真将所提算法与传统滑模观测器算法对比,并对所提算法进行实验验证。仿真与实验结果表明该算法能够准确跟踪转子的速度和位置,验证了所提算法的正确性与可行性。     

Performance control for interconnection of identical systems: Application to PLL network design

In this paper, the problem of the control law design for interconnected identical systems ensuring the global stability and the global performance properties is under consideration. Inspired by the decentralized control law design methodology using the dissipativity input–output approach, the problem is reduced to the problem of satisfying two conditions: (i) the condition on the interconnection and (ii) the condition on the local subsystem dynamics. Both problems are efficiently solved applying a (quasi‐) convex LMI optimization and standard H_∞ synthesis. The proposed design methodology is applied to the control law design of a synchronous PLL network. Copyright © 2014 John Wiley & Sons, Ltd.