用于电弧检测的电力专用SoC设计

针对传统的电弧电路故障检测结果不准确的问题,设计用于电弧检测的SoC系统,并且在55nm工艺下进行流片验证。采用包含两种结构的模数转换器的片上电压源,设计了锁相环以及复位电路,精度最高可达8.67 bit。验证结果表明,本设计可提高电弧检测的准确性。     

2020年电子电路技术热点

文章归纳了2020年电子电路产业一些技术热点,主要有5G电路板设计和基材,制造方面半加成法、3D打印、直接金属化孔电镀和垂直互连结构等技术,以及集成电路封装载板技术。     

高阶表面结构刚挠结合印制板制作技术

高阶表面结构刚挠结合印制电路板集合了混压设计,不对称设计等特点,且挠性板在外层,导致开窗处高度差较大,这一特点给制作增添了较大难度。本文选取此类典型刚挠结合板产品,分享部分关键制作技术。     

Unity direct chain with feedback series impedance based innovative negative group delay circuit

An innovative negative group delay (NGD) circuit theory on unity direct chain (UDC) topology is developed in this paper. The NGD UDC cells are based on the operational amplifier adder with feedback series impedance. Innovative topologies of high-pass NGD UDC cell composed of RL-series network, all-pass RC-parallel network and low-pass RC-series network are identified. It is a first time that all-pass NGD original topologies are defined. NGD analyses and synthesis methods of each NGD UDC cells are provided. The UDC cell based NGD functions are validated with SPICE simulations. The proofs-of-concept (POC) of UDCs behave as all-pass and low-pass NGD functions with group delay equal to −1 ms at very low frequencies. The low-pass NGD cut-off frequency is 424 Hz. The high pass NGD circuit generates −1 µs at the optimal NGD frequency of about 5.15 kHz. Further analysis of the operational amplifier gain and bandwidth effects is performed. The operational amplifier gain affects significantly the NGD level and bandwidth for the all considered UDC cells. Nevertheless, only the RC-parallel feedback based UDC cell is particularly sensitive to the operational bandwidth.     

Stumped nature hyperjerk system with fractional order and exponential nonlinearity: Analog simulation,bifurcation analysis and cryptographic applications

This article presents the construction and consumption of hyperjerk system having chaotic nature with the commensurate ordered fractional derivative on rapidly digitalized emerging technologies. The system analyzed analytically using Lipschitz condition and numerically with the help of predictor corrector approaches. Originality of constructed system is confirmed using log error plots which gives satisfactory small values on finite time scale. The dynamical performances of the complex system are termed in multiple phase planes by the mean of their significant nature. Stability and bifurcation analysis around the fractional derivative is also studies for the various parameter of system to check the visibility of chaotic solution. The system is also designed in analog circuit simulator with the aid of operational amplifier, anti-parallel semiconductor diodes for validation of the system. With the help of random number generators (RNGs), binary array generated from the hyperjerk system and plugged in to the NIST 800–22 test suite to measure the randomness. The array having high randomness is used as strong cypher key for the cryptographic execution straightforwardly in both direction encryption and decryption.     

Engineering knowledge formalization and proposition for informatics development towards a CAD-integrated DfX system for product design

Target design methodologies (DfX) were developed to cope with specific engineering design issues such as cost-effectiveness, manufacturability, assemblability, maintainability, among others. However, DfX methodologies are undergoing the lack of real integration with 3D CAD systems. Their principles are currently applied downstream of the 3D modelling by following the well-known rules available from the literature and engineers’ know-how (tacit internal knowledge).This paper provides a method to formalize complex DfX engineering knowledge into explicit knowledge that can be reused for Advanced Engineering Informatics to aid designers and engineers in developing mechanical products. This research work wants to define a general method (ontology) able to couple DfX design guidelines (engineering knowledge) with geometrical product features of a product 3D model (engineering parametric data). A common layer for all DfX methods (horizontal) and dedicated layers for each DfX method (vertical) allow creating the suitable ontology for the systematic collection of the DfX rules considering each target. Moreover, the proposed framework is the first step for developing (future work) a software tool to assist engineers and designers during product development (3D CAD modelling).A design for assembly (DfA) case study shows how to collect assembly rules in the given framework. It demonstrates the applicability of the CAD-integrated DfX system in the mechanical design of a jig-crane. Several benefits are recognized: (i) systematic collection of DfA rules for informatics development, (ii) identification of assembly issues in the product development process, and (iii) reduction of effort and time during the design review.     

一起变压器过励磁保护动作的试验及仿真分析

对一起由电容式电压互感器二次电压异常造成500k V主变跳闸的事件进行了研究和分析,对电容式电压互感器进行了故障模拟试验和仿真分析,找到了故障原因,并提出了运行维护的措施和建议。     

Linear circuits: a measurement‐based approach

This paper proposes a new measurement‐based approach that can solve synthesis problems in unknown linear circuits. The method makes use of a small number of measurements to determine the functional dependency of any circuit signal or variable on any set of design variables. Once the functional dependency is obtained, the design requirements can be applied to find the design parameter values. The results are described for linear direct current and alternating current circuits. Copyright © 2013 John Wiley & Sons, Ltd.     

8位高速低功耗流水线型ADC的设计技术研究

采用7级子ADC流水线结构设计了一个8位80MS/s的低功耗模数转换电路。为减小整个ADC的芯片面积和功耗,改善其谐波失真和噪声特性,重点考虑了第一级子ADC中MDAC的设计,将整个ADC的采样保持电路集成在第一级子ADC的MDAC中,并且采用逐级缩放技术设计7级子ADC的电路结构,在版图设计中考虑每一级子ADC中的电容及放大器的对称性。采用0.18μm CMOS工艺,该ADC的信噪比（SNR）为53dB,有效位数（ENOB）为7.98位,该ADC的芯片面积只有0.56mm2,典型的功耗电流仅为22mA。整个ADC性能达到设计要求。