Study of fin tapering effect in nanoscale symmetric dual-k spacer (SDS) hybrid FinFETs

Symmetric Dual-k Spacer (SDS) Hybrid FinFETs is a novel device, which combines three significant technologies i.e., 2-D ultra-thin-body (UTB), 3-D FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. For the first time, this article systematically analyzes the impacts of non-rectangular fin shape on various performance metrics of SDS Hybrid FinFETs. Under distinctive inclination fin angles as prescribed by the process technology, the performances of the device at different fin heights are examined. This work evaluates the response of fin tapering as well as fin height on parameters like threshold voltage (V_th), subthreshold slope (SS), on current (I_on), transconductance (g_m), transconductance generation factor (TGF), and total gate capacitance (C_gg) in SDS Hybrid FinFETs. Optimum structural configuration is thus proposed to fabricate the hybrid device in sub-20 nm FinFET architecture.     

An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering

An analytical model of CGAA MOSFET incorporating material engineering, channel engineering and stack engineering has been proposed and verified using ATLAS 3D device simulator. A comparative study of short channel effects for various device structures has also been carried out incorporating the effect of drain induced barrier lowering (DIBL), threshold voltage lowering and degradation of subthreshold slope. The effectiveness of applying the three region doping profile concept in the channel such as high-medium-low and low-high-low and its comparison with Gaussian doping profile to the cylindrical GAA MOSFET has been examined in detail. Reduced SCEs have been evaluated in combined designs i.e. TM–GC–GS, GCGS and DM–GC–GS. Out of several design engineering, GC–GS CGAA gives nearly ideal subthreshold slope whereas TM–GC–GS CGAA provides overall superior performance to reduce SCEs in deep nano-meter. The results so obtained are in good agreement with the simulated data which validate the model.     

Sampled-data modelling and analysis of the power stage of PWM DC-DC converters

The power stage of the PWM DC–DC converter is modelled and analysed using the sampled-data approach. The work addresses both continuous and discontinuous conduction mode under voltage mode control, and continuous conduction mode under current mode control. For each configuration, nonlinear and linearized sampled-data models, and control-to-output transfer functions are derived. Using this approach, both current mode control and discontinuous conduction mode can be handled systematically in a unified framework, making the modelling for these cases simpler than with the use of averaging. The results of this paper are similar to results of Tymerski, but they are presented in a simpler manner tailored to facilitate immediate application to specific circuits. It is shown how sampling the output at certain instants improves the obtained phase response. Frequency responses obtained from the sampled-data model are more accurate than those obtained from various averaged models. In addition, a new (‘lifted’) continuous-time switching frequency-dependent model of the power stage is derived from the sampled-data model. Detailed examples illustrate the modelling tools presented here and also provide a means for comparing results obtained from the sampled-data approach with those obtained from averaging.     

裂变产物~(147)Pm在体内蓄积的放射遗传毒理效应研究

本研究观察了当机体摄入不同放射量裂变产物~(147)Pm时的体内选择性蓄积部位骨髓细胞染色体畸变、姐妹染色单体互换(SCE)频率和微核率变化的诱发效应。实验结果表明,小剂量~(147)Pm以诱发骨髓细胞染色单体型畸变为主。而随着~(147)Pm摄入量的增加,可出现染色体断裂和易位。~(147)Pm摄入量与骨髓细胞染色体畸变率之间呈半对数直线效应关系,拟合的对数回归方程式为:Y=10.69+1.435InX。同时骨髓畸变细胞与~(147)Pm摄入量之间亦呈现线性关系,拟合的方程式为:Y=9.61+1.24InX,~(147)Pm内污染机体后,可诱发骨髓细胞SCE率和微核的阳性率明显升高,且随着~(147)Pm摄入量的加大,微核阳性率亦进一步增升。     

Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity,short channel effects (SCEs),leakage currents,device variability and reliability etc.Nowadays,multigate structure has become the promising candidate to overcome these problems.SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs),because of its more effective gate-controlling capabilities.In this paper,our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length.Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility,electric field,electric potential,sub-threshold slope (SS),ON current (Ion),OFF current (Ioff) and Ion/Ioff ratio.The potential benefits of SOI FinFET at drain-to-source voltage,VDS =0.05 V and VDS =0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (Av),output conductance (gd),trans-conductance (gm),gate capacitance (Cgg),and cut-off frequency (fT =gm/2πCgg) with spacer region variations.     

Nanoscale triple-gate FinFET design considerations based on an analytical model of short-channel effects

In this paper,a three-dimensional(3-D)analytical model for short-channel effects(SCEs)in a nanoscale triple-gate(TG)FinFET is derived based on solving a boundary value problem using the 3-D Poisson’s equation.This model is validated using 3-D numerical simulations(TCAD Sentaurus).Results show that SCEs in a TG FinFET can be controlled by reducing either the fin thickness(D)or height(H).On the other hand,when fixing the drive capability of turn-on current,i.e.fixing the total width of the conductive channel,and changing the ratio of D and H,there exists a case where SCEs are worst,and SCEs can be reduced by either increasing or decreasing the ratio from the worst case.This SCEs model can be used to predict the minimum channel length(Lmin)of a device when D,H,and tox are fixed,while keeping SCEs at a tolerable level.Based on the analytical model,the insights into the physics of SCEs in nanoscale TG FinFET are discussed,and design considerations are investigated.     

A bilayer graphene nanoribbon field-effect transistor with a dual-material gate

This paper introduces dual-material gate (DMG) configuration on a bilayer graphene nanoribbon field-effect transistor (BLGNRFET). Its device characteristics based on nonequilibrium Green׳s function (NEGF) are explored and compared with a conventional single-material gate BLGNRFET. Results reveal that an on-off ratio of up to 10 is achievable as a consequence of both higher saturation and lower leakage currents. The advantages of our proposed DMG structure mainly lie in higher carrier transport efficiency by means of enhancing initial acceleration of incoming carriers in the channel region and the suppression of short channel effects. Drain-induced barrier lowering, subthreshold swing and hot electron effect as the key short channel parameters have been improved in the DMG-based BLGNRFET.     

Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma based junctionless transistor

A junctionless transistor (JLT) having high doping concentration of the channel, suffers from the threshold voltage roll-off because of random dopant fluctuation (RDF) effect. RDF has been minimized by using charge plasma based JLT. Charge plasma is same as a workfunction engineering in which work function of the electrode is varied to create hole/electron plasma and induce doping in the intrinsic silicon. N-type doping is induced at the source and drain side due to difference of workfunction of silicon wafer. In this paper, charge plasma based junctionless MOSFET on selective buried oxide (SELBOX-CPJLT) is proposed. This approach is used to reduce the self-heating effect presented in SOI-based devices. The proposed device shows better thermal efficiency as compared to SELBOX-JLT. 2D-Atlas simulation revealed the electrostatics and analog performance of both the devices. The SELBOX-CPJLT exhibits better electrostatic performance as compared to SELBOX-JLT for the same channel length. The analog performance such as intrinsic gain, transconductance generation factor, output conductance and unity gain cut-off frequency are extracted from small signal ac analysis at 1 MHz and compared to SELBOX-JLT. The analysis of the thermal circuit model of SELBOX structure is also performed.     

Analytical threshold voltage and subthreshold swing model for TMG FinFET

An analytical modelling of the subthreshold surface potential, threshold voltage (V_T) and subthreshold swing (SS) for a triple material gate (TMG) FinFET is presented. The basis of the 3D solution is two separate 2D solutions. The FinFET is separated into two 2D structures: asymmetric triple material double gate (TMDG) and symmetric TMDG MOSFETs. Their potential distributions are obtained by solving the corresponding 2D Poisson’s equations. The potential distribution in TMG FinFET is obtained by a parameter-weighted sum of the two 2D solutions. Utilising the concept of minimum source barrier as the leakiest channel path, the minimum value of the surface potential is developed from the potential model. This leads to the derivations for the threshold voltage and SS. Furthermore, the effects of variation in gate work function and gate length are investigated for analytically developed SS and V_T models. Our models are validated against TCAD Sentaurus-simulated results and found to be quite accurate.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.