A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM

Technology enhancement has increased sensitivity of process variations of scaled SRAM on the verge of instability. This demands a process variation (PV) aware stability model for the modern SRAM. This paper first analyzes PV severity on readability, writability and static leakage current and provides a statistical model. The paper further improves the proposed model by using curve fitting method for stability modeling and modified Least Mean Square with first order differentiation to extract best fitting parameters. The resulting model exhibits characteristics of standard current voltage equation based model. A evolutionary optimization technique is proposed to achieve optimal cell dimension for process tolerant SRAM. The resulting SRAM is tested for worst case stability analysis using Gaussian distribution based statistical approach. Simulation results show that the resulting optimized SRAM improves read, standby and word line write margins by 4%, 4% and 23%, respectively.     

Modeling the threshold voltage of PNIN SSOI tunnel field‐effect transistor

In this paper, a physically based analytical threshold voltage model for PNIN strained‐silicon‐on‐insulator tunnel field‐effect transistor (PNIN SSOI TFET) is proposed by solving the two‐dimensional (2D) Poisson equation in narrow N⁺ layer and intrinsic region. In the proposed model, the effect of strain (in terms of equivalent Ge mole fraction), narrow N⁺ layer and gate dielectric, and so on, is being considered. The validity of the proposed model is verified by comparing the model results with 2D device simulation results. It is demonstrated that the proposed model can correctly predicts the trends in threshold voltage with varying the device parameters. This proposed model can be effectively used to design, simulate, and fabricate the PNIN SSOI TFETs with the desired performance. Copyright © 2015 John Wiley & Sons, Ltd.     

Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI

In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB scheme, simulations show that more than 30% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. We show that the OBB approach can be applied easily to a given circuit just based on the information provided by a logic simulation of the circuit (or even an analysis of its structure) and simple electrical simulations of the pMOS and nMOS transistors. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits.     

NBTI alleviation on FinFET-made GPUs by utilizing device heterogeneity

Recent experimental studies reveal that FinFET devices commercialized in recent years tend to suffer from more severe NBTI degradation compared to planar transistors, necessitating effective techniques on processors built with FinFET for endurable operations. We propose to address this problem by exploiting the device heterogeneity and leveraging the slower NBTI aging rate manifested on the planar devices. We focus on modern graphics processing units in this study due to their wide usage in the current community. We validate the effectiveness of the technique by applying it to the warp scheduler and L2 cache, and demonstrate that NBTI degradation is considerably alleviated with slight performance overhead.     

硅离子注入引入纳米晶对SIMOX材料进行总剂量辐射加固

本研究工作采用硅离子注入和高温退火工艺对SIMOX材料的BOX层进行总剂量辐射加固.辐射实验结果证明了该加固方法的有效性.PL谱和HRTEM图像显示了硅离子注入及退火工艺在材料的BOX层中引入了Si纳米晶,形成电子陷阱能级,有效俘获电子,从而提高了材料BOX层的抗总剂量辐射能力.     

FinFET for high sensitivity ion and biological sensing applications

A double-gate (DG) fin field effect transistor (FinFET) is discussed as new label-free ion and biological sensor. Simulations as function of channel doping, geometrical dimensions, operation point and materials investigated the device response to an external potential difference which provides a body threshold voltage modulation. The simulation results presented in this work clearly state the key features for an ultrasensitive FET based sensor: an enhancement low doped and partially gated transistor operating in weak-moderate inversion regime. The optimized sensitivity, obtained when the width of the fin is equal to the gate height (w_NW ∼ h_g), reaches a value of 85% for an extraction current, I_d, of 0.1 μA. These results pave the way for the fabrication process of an innovative CMOS compatible sensing system.     

Performance of (1 1 0) p-channel SOI-MOSFETs fabricated by deep-amorphization and solid-phase epitaxial regrowth processes

The impact of local deep-amorphization (DA) and subsequent solid-phase epitaxial regrowth (SPER) are studied for the co-integration of devices with hybrid surface orientation. Thin-body p-channel transistors with 20 nm thick film and HfO₂ gate insulator/metal gate along several directions on a (1 1 0) substrate were fabricated and characterized. No deterioration of transconductance or threshold voltage was induced by DA/SPER process. Device co-integration using DA/SPER process is therefore a realistic option. 〈1 1 0〉 channel on (1 1 0) SOI film yields a 200% gain on the current for the (1 0 0) surface orientation. However, the benefit of it decreases with the channel length.     

SOI LIGBT抗闩锁效应的研究与进展

概述了绝缘层上硅横向绝缘栅双极晶体管(SOI LIGBT)抗闩锁结构的改进历程,介绍了从早期改进的p阱深p+欧姆接触SOI LIGBT结构到后来的中间阴极SOI LIGBT、埋栅SOILIGBT、双沟道SOI LIGBT、槽栅阳极短路射频SOI LIGBT等改进结构;阐述了一些结构在抗闩锁方面的改善情况,总结指出抑制闩锁效应发生的根本出发点是通过降低p基区电阻的阻值或减小流过p基区电阻的电流来削弱或者切断寄生双极晶体管之间的正反馈耦合。     

单模光纤与SOI纳米线波导耦合设计

波导光栅在集成光学发展中扮演着重要的角色。与其他的耦合方法相比,光栅耦合器具有耦合效率高、制备封装成本低、无需芯片端面抛光、可以在任何地方实现信号输入输出等优点,成为纳米光波导最有潜力的耦合方法。本文提出利用OPTIFDTD软件仿真结合MATLAB编程的方法精确计算光栅耦合效率的新方法。仿真分析了光栅的周期、槽深、占空比、SiO2层厚度等光栅参数对耦合效率的影响,并给出了使输入光栅耦合器耦合效率达到42.6%;输出光栅耦合器的耦合效率达到72.3%的一组最佳光栅参数。     

SOINMOSFET的双峰及辐射效应研究

通过对SOINMOFET的总剂量辐照试验,对器件辐照中的双峰效应进行研究。文中给出了双峰效应的表征。试验结果表明双峰的形状随辐照总剂量的增加而改变,并分析了具体的原因。另外,背栅晶体管对主要晶体管的耦合效应要远远大于其对寄生晶体管的作用。