Electrochemical capacitance-voltage characterization of plasma-doped ultra-shallow junctions

Ultra-shallow Si p⁺n junctions formed by plasma doping are characterized by electrochemical capacitance-voltage (ECV). By comparing ECV results with those of secondary ion mass spectroscopy (SIMS), it is found that the dopant concentration profiles in heavily-doped p⁺ layer as well as junction depths measured by ECV are in good agreement with those measured by SIMS. However, the ECV measurement of dopant concentration in the underlying lightly doped n-type substrate is significantly influenced by the upper heavily-doped layer. The ECV technique is also easy to control and reproduce. The ECV results of ultra-shallow junctions (USJ) formed by plasma doping followed by different annealing processes show that ECV is capable of reliably characterizing a Si USJ with junction depth as low as 10 nm, and dopant concentration up to 10²¹ cm⁻³. Also, its depth resolution can be as fine as 1 nm. Therefore, it shows great potential in application for characterizing USJ in the sub-65 nm technology node CMOS devices. __________ Translated from Chinese Journal of Semiconductors, 2006, 27(11): 1966–1969 [译自: 半导体学报]     

Influence of bias-temperature stressing on the electrical characteristics of SiOC:H film with Cu/TaN/Ta-gated capacitor

Experiments on bias-temperature stressing, capacitance-voltage measurements, current-voltage characteristics, and time-dependent dielectric breakdown were performed to evaluate the reliability of Cu and low-k SiOC:H integration. A high leakage current of ∼8 × 10⁻¹⁰ to 2 × 10⁻⁸ A/cm² at 1 MV/cm in SiOC:H dielectrics in a Cu-gated capacitor, and a lower 2 × 10⁻¹⁰ to 5 × 10⁻¹⁰ A/cm² at 1 MV/cm in a Cu/TaN/Ta-gated capacitor, were observed at evaluated temperatures. The drift mobility of the Cu⁺ ions in the Cu/TaN/Ta-gated capacitor was lower than that in a Cu-gated capacitor. A physical model was developed to explain the observed kinetics of Cu⁺ ions that drift in Cu-gated and Cu/TaN/Ta-gated capacitors. The electric field in the Cu-gated MIS capacitor in the cathode region is believed to be increased by the accumulation of positive Cu⁺ ions, which determines the breakdown acceleration. Good Cu⁺ ions drift barrier layers are required as reliable interconnects using thin TaN and Ta layers. Additionally, Schottky emission dominates at low electric fields, E<1.25 MV/cm, and Poole-Frenkel emission dominates at high fields, E>1.5 MV/cm.     

电化学电容-电压法表征等离子体掺杂超浅结

采用电化学电容-电压(ECV)法对等离子体掺杂制备的Si超浅p n结进行了电学表征.通过对超浅p n结样品ECV测试和二次离子质谱(SIMS)测试及比较,发现用ECV测试获得的p 层杂质浓度分布及结深与SIMS测试结果具有良好的一致性,但ECV测试下层轻掺杂n型衬底杂质浓度受上层高浓度掺杂影响很大.ECV测试具有良好的可控性与重复性.对不同退火方法等离子体掺杂形成的超浅结样品的ECV系列测试结果表明,ECV能可靠地表征结深达10nm,杂质浓度达1021cm-3量级的Si超浅结样品,其深度分辨率可达纳米量级,它有望在亚65nm节点CMOS器件的超浅结表征中获得应用.     

TiN and TaN diffusion barriers in copper interconnect technology: Towards a consistent testing methodology

The present status of work on diffussion barriers for copper in multilevel interconnects is surveyed briefly, with particular emphasis on TiN and TaN, and silicon dioxide as the interlayer dielectric. New results are presented for these materials, combining thermal annealing and bias temperature stress testing. With both stress methods, various testing conditions are compared using capacitance-vs-voltage (C-V) and leakage current-vs-voltage (I-V) measurements to characterize the stressed samples. From an evaluation of these data and a comparison with other testing approaches, conditions for a consistent testing methodology of barrier reliability are outlined.     

Development of a triangular-plate MEMS tunable capacitor with linear capacitance-voltage response

This paper introduces a modified structure for parallel-plate-based MEMS tunable capacitors. The capacitor has triangular electrodes with geometric and structural asymmetry, which enhances its performance. The device structure is also equipped with a set of cantilever beams between capacitor’s electrodes, called middle beams. These beams provide extra stiffness as tuning voltage increases and delay the pull-in which results in a higher tunability. They also reduce the high sensitivity of the capacitance to the voltage change and linearize the C-V response. An analytical model is developed to optimize the capacitor’s dimensions for maximum linearity of the response. Numerical simulations demonstrate tunabilities over 150% where more than 2/3 of which is highly linear. Capacitors fabricated with PolyMUMPs verify that the design technique proposed in this paper can improve the linearity of the device and increase the maximum tunability. The proposed design has a simple geometry and is fabricated using three structural layers, and therefore, it can be easily integrated in tunable filters or other RF circuits.     

表面预处理对InSb钝化层界面的影响

本文介绍了采用不同的方法对InSb表面进行表面预处理,来改善InSb钝化膜层的电学性能。通过对InSb MIS结构进行C-V测试来评价不同方法预处理制备的钝化结构的电学特性。结果表明等离子预处理能明显改善InSb衬底和钝化层之间的界面性能,尤其是选用N2O等离子预处理InSb衬底表面,在控制界面陷阱和减少钝化层固定电荷方面,效果更明显,有利于提高InSb红外器件的可靠性。     

New surface treatment method for improving the interface characteristics of CdTe/Hg1−xCdxTe heterostructure

This paper presents a new simple method of HgCdTe surface treatment which consists of chemical oxidation of HgCdTe with nitric acid and removal of the oxide with ammonium hydroxide. The electrical properties of the electron-beam deposition CdTe passivation of Hg_0.7Cd_0.3Te are investigated with regard to the effects of HgCdTe surface etching, exposure to nitric acid, and the new surface treatment method. As the HgCdTe surface is progressively etched with bromine in methanol (Br-MeOH), the surface becomes rougher and a higher density of fixed charge is induced at the interface between CdTe and HgCdTe. Exposure to HNO₃ results in a very high density of fixed charge and performance degradation in metal insulator semiconductor (MIS) capacitors, which is due to the chemical oxide grown by HNO₃. The oxide growth rate is enhanced as the concentration of HNO₃ increases or as more H₂O is added. This oxide can be removed with NH₄OH. After the new surface treatment, MIS capacitors of Hg_0.7Cd_0.3Te show substantial improvement in electrical properties, such as low density of fixed charge and reduced hysteresis width, regardless of previous surface etching.     

Schottky barrier height studies of Au/4H-SiC(0001) using photoemission and synchrotron radiation

The Schottky barrier height (SBH) of Au on 4H-SiC(0001) has been studied using photoemission and synchrotron radiation. The Au was deposited in-situ on clean and well-ordered √3×√3 R30° reconstructed SiC surfaces prepared by in situ heating at ∼950°C. The SBH was determined from the shift observed in the Si 2p core level, in addition to the initial band bending determined for the clean surface. The results were compared with values obtained by electrical, capacitance-voltage (C-V), and current-voltage (I-V) characterization methods. A favorable comparison between the three independent, SBH determination methods was found.     

Determination of capacitance-voltage characteristics of organic semiconductor devices by combined current-voltage and voltage decay measurements

We present in this paper a new method,based on measurements of conventional direct current-voltage(I-V) characteristics and transient voltage-time(V-t) characteristics during the discharge process,for determining capacitance-voltage(C-V) characteris-tics of organic semiconductor devices.Derivatives of I-V and V-t,dI/dV and dV/dt,are related with C by a simple formula C=-V(dI/dV)/(dV/dt)The validity of the method is confirmed by experimental data measured from a set of single-organic-layer devices with diffe...     

Studies on Al<Subscript>2</Subscript>O<Subscript>3</Subscript>/ZrO<Subscript>2</Subscript>/Al<Subscript>2</Subscript>O<Subscript>3</Subscript> high K gate dielectrics applied in a fully depleted SOI MOSFET

Al₂O₃/ZrO₂/Al₂O₃ gate stacks were prepared on ultrathin SOI (Silicon on insulator) substrates by ultrahigh vacuum electron beam evaporation and post-annealed in N₂ at 450°C for 30 min. Three clear nanolaminate layered structure of Al₂O₃(2.1 nm)/ZrO₂(3.5 nm)/Al₂O₃(2.3 nm) was observed with a high-resolution cross-sectional transmission electron microscope (HR-XTEM). High frequency capacitance voltage (C-V) characteristics of a fully depleted (FD) SOI MOS capacitor at 1 and 5 MHz were studied. The minority carriers determine the high frequency C-V properties, which is opposite to the case of bulk MOS capacitors. The series resistance of the SOI substrate is found to be the determinant factor of the high frequency characteristics of FD SOI MOS capacitors. This article is based on a presentation in “The 7th Korea-China Workshop on Advanced Materials” organized by the Korea-China Advanced Materials Cooperation Center and the China-Korea Advanced Materials Cooperation Center, held at Ramada Plaza Jeju Hotel, Jeju Island, Korea on August 24≈27, 2003.