一种新型大功率无损缓冲Buck变换器的研究

提出了一种优化的高速电机驱动电路。在传统的三相逆变电路前端加入多路交错并联的无损缓冲Buck变换器,实现了开关管的零电流开通(ZCS)、零电压关断(ZVS),从而解决了高开关频率下的损耗问题,提高了系统的效率及可靠性。同时多路无损缓冲电路共用一个二极管和电感,可有效减小变换器体积,提高功率密度。详细分析了该变换器的原理,并通过实验验证了分析和设计的正确性和可行性。     

光伏交错反激逆变器解耦控制方法的研究

交流光伏模块将光伏组件与微型逆变器集成为一体,构成一个可直接与电网或负载连接的光伏发电系统模块。微型逆变器独立控制每一个光伏组件,因此受到外部环境条件变化影响小,光伏电池的利用率优于其他光伏并网发电系统结构。首先,介绍了交错式反激逆变器的拓扑结构、工作原理以及并网控制技术;再对3种主动式功率解耦方式及控制方法进行了比较;仿真分析结果表明,3种功率解耦方式能够有效抑制二倍频功率扰动,提高了光伏电池板的效率,可延长电容寿命,但同时增加了设备的体积和成本,逆变效率也会相应下降,电路拓扑和控制都变得复杂。     

一种高精度时钟同步电路

本文提出了一种基于交错延迟单元和动态补偿电路的高精度时钟同步电路结构,HPSC,并 可用在对时钟要求较高的大规模分布网络中。此电路采用了基于SMD的粗调结构和动态补偿 电路的细调结构,可在两个时钟周期内完成粗调并在接下来三个时钟周期内完成细调,其误 差小于3.8 ps。本电路使用SMIC 0.13 μm 1P6M 工艺设计并实现,供电电压1.2 V。其输入 频率为200MHz-800MHz,占空比为20%-80%,有效面积 245μm×134μm,功耗为1.64 mW@500MHz     

A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications

In this paper, a dynamically reconfigurable, Non-overlap Rotational Time Interleaved (NRTI) switched capacitor (S-C) DC-DC converter is presented. Its S-C module is reconfigurable to generate three different fractions (viz., 1/3, 1/2 and 2/3) of its input supply (Vdd). This maintains good power efficiency while its output voltage gets adjusted over a large range. In addition, a load-current-sensing circuit is integrated within it to dynamically reconfigure the S-C module based on the required driving capability. This feature enables to extend load current range to higher limit and at the same time improves the power efficiency in low load current regime. The S-C module is integrated with a current control loop for load and line regulation.The proposed architecture is simulated in a 0.18 μm CMOS process using dual oxide transistors to demonstrate the efficacy of the proposed topology. The input supply voltage is 3.3 V and the regulated output range is 0.8-1.6 V. Total flying capacitance is 330 pF and the load capacitor value is 50 pF. For an output of 1.35 V, its power efficiency is maintained above 50% over a load current range of 4 -17.6 mA with a peak of 66% at 9 mA. Throughout this current range the output voltage ripple remains within 12 mV.     

交错并联Buck中耦合电感的设计

针对开关电源系统对功率密度等级不断提高的要求,为进一步发挥交错并联技术的优势,本文以减小输出电流纹波和改善动态特性为目标,对大占空比条件下交错并联Buck电路中的耦合电感进行了详细分析和计算。通过软件仿真验证,得出了耦合系数和占空比对电路性能的具体影响,耦合系数的取值应尽量接近-1,从而为耦合电感的设计提供了理论依据。     

联网微型光伏逆变器分段混合控制方法研究

针对交错反激微型光伏逆变器在临界电流连续模式(BCM)控制下开关管频带宽、控制复杂和在电流断续模式(DCM)控制下变压器功率转换密度低、并网电流质量差等问题,提出了一种分段混合控制方法。该控制方法对微逆变器的工作周期进行了分段,使微逆变器在单个反激式的电流断续模式下和交错反激式的临界电流连续模式下交替工作。详细分析了分段混合控制下交错反激变换器产生正弦电流的原理,给出了具体实现方案的开关序列和波形。研究结果表明,分段混合控制方法作用下联网微逆变器可实现与电网电压同频、同相的并网电流输出,并提高微逆变器工作效率和功率转换量,该控制方法适合于微逆变器的各个功率等级。     

A segment‐based sparse matrix–vector multiplication on CUDA

The challenge for Sparse Matrix–Vector multiplication (SpMV) performance is memory bandwidth, which mostly depends on input matrices and underlying computing platforms. To solve this challenge, many researchers have explored a variety of optimization techniques. One of the most promising aspects focuses on designing storage formats to represent sparse matrices. However, lots of prior storage formats cannot fully take advantage of the underlying computing platforms, resulting in unsatisfactory performance and large memory footprint. Therefore, a novel storage format, called Segmented Hybrid ELL + Compressed Sparse Row (CSR) (SHEC for short), is proposed to further improve the throughput and lessen memory footprint on Graphics Processing Unit (GPU). SHEC format employs an interleaved combination pattern, which combines certain amount of compressed rows to form a new SHEC row. Segmentation is brought in to balance load and reduce memory footprint. According to the empirical data, an automatic SHEC‐based SpMV is developed to fit for all the matrices. Experimental results show that SHEC approach outperforms the best results of NVIDIA SpMV library and exhibits a comparable performance with state‐of‐the‐art storage formats on the standard dataset. Copyright © 2012 John Wiley & Sons, Ltd.     

Coding Schemes Incorporating Soft-Decision DPSK over HF Rayleigh Fading Channels

A soft-decision 8-DPSK modulation format is introducedin a concatenated coding scheme and the performance of the resultingsystem is evaluated over a slow Rayleigh fading HF ionospheric link inthe presence of Additive White Gaussian noise (AWGN). Well-known UngerboeckTCM techniques are used as inner codes and a Reed–Solomon blockcode as outer code. The coded/modulated signal is differentially encodedbefore transmission to combat random phase changes caused by the channel.Soft-decision demodulator's output is used as an input to a modifiedViterbi decoder that calculates the Euclidean distances of the receivedsignal from an 8-PSK constellation adapted to the signal's amplitudevariations. Block interleaving techniques are necessary to randomise longbursts of errors caused by the fading channel. Simulation results showthat significant coding gains are achieved with a minor bandwidth expansionover uncoded, diversity or other coded systems. Finally, theinteresting effects of interleaving on the performance of the proposedsystems are analysed.     

基于FAN9612控制IC的交错双BCMPFC升压变换器设计

介绍了交错双BCMPFC控制器FAN9612的特点及基于FAN9612的400W交错BCM升压PFC变换器设计。     

一种新型交错并联Boost-Flyback直流升压变换器

光伏/燃料电池发电系统的前级输出电压低,为提高输出电压通常需要高升压比直流变换器。针对这一问题,提出了一种新的交错并联Boost-Flyback变换器(interleaved Boost-Flyback converter,IBFC)。该变换器采用Boost与Flyback变换器交错并联的方式来减小输入输出纹波,并利用Flyback变换器的变压器匝比来获得较高的电压增益。Flyback变换器的变压器主边通过电容与输出端相连接,可将输入侧漏感能量转移到输出,减小了漏感损耗。变换器中间的储能电容极大减小了开关管的电压应力,进一步提高了转换效率。分析了IBFC的各种工作状态,推导了各元件的电压应力。实验结果验证了变换器的可行性。