High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

一种适用于开关电容电路的MOS开关栅增压电路

提出了一种新的MOS器件栅增压电路,它在减小MOS开关导通电阻的同时,减少了衬偏效应以及MOS开关输出信号的失真. 该电路采用了0.13μm 1.2V/2.5V CMOS工艺,HSPICE的仿真结果表明该栅增压电路适用于高速低电压开关电容电路.     

平面栅SiC MOSFET设计研究

碳化硅MOSFETs开关速率快,耐压高,在逆变器应用领域前景广阔。平面栅MOSFETs因其成熟的工艺是最先被商业化的器件。在平面栅MOSFETs的设计中,降低导通电阻和提高芯片的电流密度是重要的开发目标。基于自主研制的1 200 V及1 700 V SiC MOSFETs,研究了载流子扩展层技术、JFET注入技术以及元胞结构对器件电学特性的影响。测试结果表明采用方形元胞设计的SiC MOSFET的电流明显大于采用条形元胞设计的电流,JFET注入对阈值电压的影响比载流子扩展层技术更小。     

表面注入D-RESURF器件耐压模型

建立表面注入双重降低表面电场(D-RESURF)结构击穿电压模型。D-RESURF器件在衬底纵向电场和Pb区附加电场的影响下,漂移区电荷共享效应增强,优化漂移区掺杂浓度增大,器件导通电阻降低。分析漂移区浓度和厚度对击穿电压的影响,获得改善击穿电压和导通电阻折中关系的途径。在满足最优表面电场和完全耗尽条件下,导出吻合较好的二维RESURF判据。在理论的指导下,成功研制出900 V的D-RESURF高压器件。     

超低比导通电阻SOI双栅槽型MOSFET

本文提出了超低比导通电阻(Ron,sp) SOI双栅槽型MOSFET(DG Trench MOSFET)。此MOSFET的特点是拥有双栅和一个氧化物槽：氧化物槽位于漂移区,一个槽栅嵌入氧化物槽,另一个槽栅延伸到埋氧层。首先,双栅依靠形成双导电沟道来减小Ron,sp;其次,氧化物槽不仅折叠漂移区,而且调制电场,从而减小元胞尺寸,增大击穿电压。当DG Trench MOSFET的半个元胞尺寸为3μm时,它的击穿电压为93V,Ron,sp为51.8mΩ?mm2。与SOI单栅MOSFET(SG MOSFET)和SOI单栅槽型MOSFET(SG Trench MOSFET)相比,在相同的BV下,DG Trench MOSFET的Ron,sp分别地降低了63.3%和33.8%。     

高压功率VDMOS元胞的研制

基于Sentaurus TCAD仿真软件,在外延层参数与生产工艺确定的情况下,通过调整元胞的多晶硅长度优化特征导通电阻,并通过对版图元胞面积的准确计算,设计了三款导通电阻目标值为2.4,3.0和3.3Ω的高压功率VDMOS芯片。流片结果显示,导通电阻的平均值与版图计算值吻合度均超过96%,表明了该设计方法、仿真参数及版图设计具有较高的可靠性。     

一种采用多个渐变反型电荷层优化电场的LDMOST

A lateral double-diffused metal-oxide-semiconductor field effect transistor （LDMOST） with multiple n-regions in the p-substrate is investigated in detail. Because of the decrescent n-regions, the electric field distribu- tion is higher and more uniform, and the breakdown voltage of the new structure is increased by 95%, in comparison with that of a conventional counterpart without substrate n-regions. Based on the trade-off between the breakdown voltage and the on-resistance, the optimal number of n-regions and the other key parameters are achieved. Furthermore, sensitivity research shows that the breakdown voltage is relatively sensitive to the drift region doping and the n-regions＇ lengths.     

多场极板LEDMOS表面电场和导通电阻研究

研究了常规LEDM O S,带有两块多晶硅场极板LEDM O S以及带有两块多晶硅场极板和一块铝场极板的LEDM O S表面电场分布情况,重点研究了多块场极板在不同的外加电压下,三种LEDM O S的表面峰值电场和导通电阻的变化情况。模拟结果和流水实验结果都表明:多块场极板是提高LEDM O S击穿电压的一种有效方法,而且场极板对导通电阻的影响很小。研究结果还表明:由于金属铝引线下面的氧化层很厚,所以铝引线几乎不会影响到LEDM O S的击穿特性。     

具有电阻场板的薄膜SOI-LDMOS的精确解析

介绍了一种对具有电阻场板的薄膜SOI LDMOS的精确解析设计方法.在对电场分析的基础上,提出了新的电离率模型,并求出了电离率积分的准确路径,进而得到击穿电压、漂移区掺杂、漂移区长度与SOI硅层厚度、埋氧层厚度的关系.模拟结果表明,解析与模拟结果具有很好的一致性,而且设计的器件具有击穿电压大、比导通电阻极小的优点.该解析理论为在薄膜SOI材料上制作性能优良的高压功率器件提供了一个很好的参考     

Power Trench MOSFETs with very low specific on-resistance for 25V applications

In this paper, an investigation of the benefits of deep ultra violet lithography for the manufacturing of Trench MOSFETs and its impact on device performance is presented. We discuss experimental results for devices with a pitch size down to 0.6 μm fabricated with an unconventional implant topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are benchmarked against previously published TrenchMOS technologies by de-embedding the parasitic substrate resistance, revealing a record-low specific on-resistance of 5.3 mΩ mm² at a breakdown voltage of 30 V (V_gs = 10 V).