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排序方式: 共有2201条查询结果,搜索用时 31 毫秒
1.
针对阵面校准中信标抖动导致相位误差超差问题,提出利用参考天线单元随动来减小相位误差的方案;同时,针对大型阵面宽带幅相修正中大盲区与高信噪比要求的矛盾,提出系留气球的解决方案。通过分析计算,证明两个解决方案在工程应用中合理可行。 相似文献
2.
针对中空和非中空触发电极结构的两间隙开关,进行了触发击穿特性实验,对比两个间隙的击穿抖动和通道数,分析了串级两间隙的相互影响机制。实验结果表明:两只开关触发间隙击穿抖动和通道数变化规律基本一致;非中空开关自击穿间隙击穿抖动随工作系数的增大而减小,最小约3 ns,中空开关自击穿间隙击穿抖动始终约1 ns;非中空开关自击穿间隙难形成多通道放电,中空开关自击穿间隙通道数明显多于其他间隙。触发间隙首先放电产生紫外光,通过触发电极中空通孔预先照射自击穿间隙产生初始电子,是自击穿间隙击穿抖动减小、通道数增加的主要作用机制。 相似文献
3.
Hoon‐Seok Jang Mannan Saeed Muhammad Tae‐Sun Choi 《Microscopy research and technique》2019,82(3):224-231
The consideration of the noise that affects 3D shape recovery is becoming very important for accurate shape reconstruction. In Shape from Focus, when 2D image sequences are obtained, mechanical vibrations, referred as jitter noise, occur randomly along the z‐axis, in each step. To model the noise for real world scenarios, this article uses Lévy distribution for noise profile modeling. Next, focus curves acquired by one of focus measure operators are modeled as Gaussian function to consider the effects of the jitter noise. Finally, since conventional Kalman filter provides good output under Gaussian noise only, a modified Kalman filter, as proposed method, is used to remove the jitter noise. Experiments are carried out using synthetic and real objects to show the effectiveness of the proposed method. 相似文献
4.
For a distributed parameter system with an input delay in the boundary, a feedback control law is presented by means of the backstepping method. The square integrability of input signal is verified based on the target system. Then, the boundedness and invertibility of the corresponding backstepping transformation are proved under the regularity of system and the admissibility of feedback operator. Thus, the resulting closed-loop system is shown to be exponentially stable. Finally, as an application, a numerical simulation of a one-dimensional Schrödinger equation with a delay input is carried out, and the simulation results demonstrate the effectiveness of the suggested control law. 相似文献
5.
A novel DSP‐based PFC‐DPLL with fuzzy controlled acquisition aid to improve acquisition performance and noise immunity 下载免费PDF全文
Basab Chatterjee B. N. Biswas Sudhbindu Ray 《International Journal of Communication Systems》2015,28(15):2051-2066
This paper proposes a new digital signal processing (DSP)‐based phase frequency controlled digital phase locked loop. Here, a very simplistic form of fuzzy logic controller with the help of carrier phase and frequency error as input data is used to provide an acquisition aid. A frequency discriminator is employed to generate frequency error, and phase detector output is taken for phase error. This addition of an acquisition aid helps the loop to achieve the minimum acquisition time and maximum noise rejection simultaneously. An additional phase control in the digitally controlled oscillator makes the loop perform even better towards this goal. The implementation of the proposed loop is carried out on a reconfigurable logic platform using System Generator®;, a tool from Xilinx®; used to design real‐time DSP application. A significant improvement of time domain characteristics are observed as well as the performance in presence of additive white Gaussian noise is demonstrated in terms of the reduction in steady‐state phase jitter and enhancement in output signal to noise ratio in the proposed loop. Copyright © 2014 John Wiley & Sons, Ltd. 相似文献
6.
Dinh Cong Huong Van Thanh Huynh Hieu Trinh 《International Journal of Adaptive Control and Signal Processing》2020,34(9):1281-1293
This article considers the design of interval functional observers to estimate a linear function of the state vector of time-delay systems subject to both input and output additive disturbances. Two novel functional observers are proposed and designed such that they bound the set of all admissible values of a linear function of the state vector at each instant of time. By contrast to interval observers currently available in the literature, both observers proposed in this article utilize multiple delayed output measurement and have a more general structure. This trade-off feature overcomes some drawbacks in previous work and enables interval functional observers to be designed for a wider class of time-delay systems. Conditions for the existence of interval functional observers are derived and an effective design algorithm for computing unknown observer matrices is provided. Two illustrative examples are given to show the advantages and effectiveness of our design method. 相似文献
7.
研究一类离散时滞切换系统基于异步切换下的混合H∞和无源模型参考跟踪控制问题。采用多Lyapunov函数理论并利用平均驻留时间方法,得到以线性矩阵不等式(LMIs)表示的时滞切换系统异步切换下指数稳定且具有混合H∞和无源模型参考跟踪性能的充分条件。最后,以仿真例验证所提出方法的正确性和有效性。 相似文献
8.
9.
智能变电站IEEE 1588同步时延优化方法 总被引:1,自引:1,他引:0
针对智能变电站时间同步过程中通信网络的路径时延抖动导致同步精度下降问题,提出一种基于IEEE 1588时间同步协议的时延优化方法。首先分析智能变电站环境下路径时延抖动同步误差过程,实现同步误差产生机理的量化分析;然后阐述所提出的同步时延优化方法,方法在IEEE 1588协议框架下实现从时钟的基本时钟补偿基础上,拓展时延测量机制获取路径时延抖动的时钟补偿最佳估计值,实现从时钟同步时间的二次时钟补偿,减少路径时延抖动对同步精度影响;最后以智能变电站中典型IEEE 1588协议端到端透明时钟同步模式搭建仿真实验验证所提方法。实验结果表明所提方法能够提高智能变电站中从时钟同步精度和稳定性。 相似文献
10.
Motahhareh Estebsari Mohammad Gholami Mohammad Javad Ghahramanpour 《International Journal of Circuit Theory and Applications》2018,46(3):401-414
In this paper, a design of analog delay locked loop is introduced in which new techniques are applied to eventually increase operating frequency range and reduce jitter considerably. In this design, all blocks of a delay locked loop including a voltage controlled delay line, charge pump, and loop filter are accurately designed. A new delay cell is proposed with wide delay range, in which increase of delay range results in using fewer cells, and consequently the power consumption will decrease. Current mirror techniques and feedback in the proposed charge pump also cause higher current matching and better jitter performance. This delay locked loop, which is designed with TSMC 0.18‐μm CMOS technology, has a wide frequency range from 217 to 800 MHz. It consumes maximum 3.4‐mW and minimum 2.6‐mW power dissipation in source voltage of 1.8 V, which is suitable for low power applications. It also has an appropriate lock time that is at least equal to 3 clock cycles at 217 MHz and at most 25 clock cycles at 800 MHz. Jitter performance in this delay locked loop is improved significantly: RMS jitter is 0.65 ps at 800 MHz and 2.54 ps at 217 MHz. Moreover, its maximum peak‐to‐peak jitter is equal to 5.17 ps, and its minimum peak‐to‐peak jitter is equal to 1.39 ps at 217 and 800 MHz, respectively. 相似文献