Low voltage operating organic light emitting transistors with efficient charge blocking layer

Charge injection/blocking layers play important roles in the performances of organic electronic devices. Their incorporation into organic light emitting transistors has been limitted, due to generally high operating voltages (above 60 V) of these devices. In this work, two hole blocking molecules are integrated into tris-(8-hydroxyquinoline) aluminum (Alq₃) based light emitting transistors under operating voltage as low as 5 V. The effects of hole blocking and electron injection are decoupled through the differences in the energy levels. Significantly improved optical performance is achieved with the molecule of suitable energy level for electron injection. Surprisingly, a decreased performance is observed in the case of another hole blocking molecule evidencing that charge injection overweighs charge blocking in this device architecture.     

High-performance 2,9-DPh-DNTT organic thin-film transistor by weak epitaxy growth method

2,9-DPh-DNTT, an isomeric of diphenyl-dinaphtho[2,3-b:2′,3′-f]-thieno[3,2-b] thiophene (DPh-DNTTs), is an emerging candidate of high mobility organic semiconductor material. In this work, a high performance 2,9-DPh-DNTT organic thin-film transistor (OTFT) is fabricated by the method of weak epitaxy growth. The quality of 2,9-DPh-DNTT thin film was significantly improved when its epitaxial layer grows on an inducing layer of para-sexiphenyl (p-6P). Continuous large-area, highly ordered and terraced 2,9-DPh-DNTT polycrystalline thin films are obtained. The hole mobility of as-fabricated 2,9-DPh-DNTT thin-film transistor reaches up to 6.4 cm² V⁻¹s⁻¹. This simple process of preparing high mobility 2,9-DPh-DNTT thin-film transistor supplies a facile route of large-area OTFT fabrication.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Using d-limonene as the non-aromatic and non-chlorinated solvent for the fabrications of high performance polymer light-emitting diodes and field-effect transistors

Aiming to environment protection, green solvents are crucial for commercialization of solution-processed optoelectronic devices. In this work, d-limonene, a natural product, was introduced as the non-aromatic and non-chlorinated solvent for processing of polymer light-emitting diodes (PLEDs) and organic field effect transistors (OFETs). It was found that d-limonene could be a good solvent for a blue-emitting polyfluorene-based random copolymer for PLEDs and an alternating copolymer FBT-Th₄(1,4) with high hole mobility (μ_h) for OFETs. In comparisons to routine solvent-casted films of the two conjugated polymers, the resulting d-limonene-deposited films could show comparable film qualities, based on UV–vis absorption spectra and observations by atomic force microscopy (AFM). With d-limonene as the processing solvent, efficient blue PLEDs with CIE coordinates of (0.16, 0.16), maximum external quantum efficiency of 3.57%, and luminous efficiency of 3.66 cd/A, and OFETs with outstanding μ_h of 1.06 cm² (V s)⁻¹ were demonstrated. Our results suggest that d-limonene would be a promising non-aromatic and non-chlorinated solvent for solution processing of conjugated polymers and molecules for optoelectronic device applications.     

In-plane light emission of organic light-emitting transistors with bilayer structure using ambipolar semiconducting polymers

The concept of using an ambipolar bilayer semiconducting heterostructure in organic light-emitting transistors (OLETs) is introduced to provide a new approach to achieve surface emission. The properties of top-gate-type bilayer OLETs with ambipolar materials based on two types of fluorene-type polymers used as an emissive layer and an electron blocking layer are investigated. Line-shaped yellow–green emission occurs near a hole-injection electrode. When hole transport is dominant in the upper layer which acts as an electron blocking layer, and electrons are injected into the lower layer, an in-plane light-emitting pattern is observed. The measured in-plane emission zone confirms that both hole and electron transport are determined to occur mainly along the different organic layers between the source and drain electrodes, and an in-plane recombination zone of electrons and holes exists near the bilayer organic interface. This work is anticipated to be useful for the development of in-plane light-emitting transistors.     

THE effect of Srandom DOPANT fluctuation on threshold voltage and drain current variation in junctionless nanotransistors

We investigate the effect of dopant random fluctuation on threshold voltage and drain current variation in a two-gate nanoscale transistor. We used a quantum-corrected technology computer aided design simulation to run the simulation (10000 randomizations). With this simulation, we could study the effects of varying the dimensions (length and width), and thicknesses of oxide and dopant factors of a transistor on the threshold voltage and drain current in subthreshold region (off) and overthreshold (on). It was found that in the subthreshold region the variability of the drain current and threshold voltage is relatively fixed while in the overthreshold region the variability of the threshold voltage and drain current decreases remarkably, despite the slight reduction of gate voltage diffusion (compared with that of the subthreshold). These results have been interpreted by using previously reported models for threshold current variability, load displacement, and simple analytical calculations. Scaling analysis shows that the variability of the characteristics of this semiconductor increases as the effects of the short channel increases. Therefore, with a slight increase of length and a reduction of width, oxide thickness, and dopant factor, we could correct the effect of the short channel.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

Assessing the width of Gaussian density of states in organic semiconductors

The Density of States (DOS) is an ingredient of critical importance for the accurate physical understanding of the optoelectronic properties of organic semiconductors. The disordered nature of this class of materials, though, renders the task of determining the DOS far from trivial. Its extraction from experimental measurements is often performed by driving the semiconductor out of thermal equilibrium and therefore requires making assumptions on the charge transport properties of the material under examination. This entanglement of DOS and charge transport models is unfavorable since transport mechanisms in organic semiconductors are themselves still subject of debate. To avoid this, we propose an alternative approach which is based on populating and probing the DOS by means of capacitive coupling in Metal Insulator Semiconductors (MIS) structures while keeping the semiconductor in thermal equilibrium. Assuming a Gaussian shape, we extract the DOS width by numerical fitting of experimental Capacitance–Voltage curves, exploiting the fact that the DOS width affects the spatial distribution of accumulated charge carriers which in turn concurs to define the MIS capacitance. The proposed approach is successfully tested on two benchmark semiconducting polymers, one of n-type and one of p-type and it is validated by verifying the robustness of the extraction procedure with respect to varying the insulator electrical permittivity. Finally, as an example of the usefulness and effectiveness of our approach, we study the static characteristics of thin film transistors based on the aforementioned polymers in the framework of the Extended Gaussian Disorder transport model. Thanks to the extracted DOS widths, the functional dependence of current on the gate voltage is nicely predicted and physical insight on transistor operation is achieved.     

Sol-gel processed high-k aluminum oxide dielectric films for fully solution-processed low-voltage thin-film transistors

High-k oxide dielectric films have attracted intense interest for thin-film transistors (TFTs). However, high-quality oxide dielectrics were traditionally prepared by vacuum routes. Here, amorphous high-k alumina (Al₂O₃) thin films were prepared by the simple sol-gel spin-coating and post-annealing process. The microstructure and dielectric properties of Al₂O₃ dielectric films were systematically investigated. All the Al₂O₃ thin films annealed at 300–600?°C are in amorphous state with ultrasmooth surface (RMS ~ 0.2?nm) and high transparency (above 95%) in the visible range. The leakage current of Al₂O₃ films gradually decreases with the increase of annealing temperature. Al₂O₃ thin films annealed at 600?°C showed the low leakage current density down to 3.9?×?10^?7 A/cm² at 3?MV/cm. With the increase of annealing temperature, the capacitance first decreases then increases to 101.1?nF/cm² (at 600?°C). The obtained k values of Al₂O₃ films are up to 8.2. The achieved dielectric properties of Al₂O₃ thin films are highly comparable with that by vapor and solution methods. Moreover, the fully solution-processed InZnO TFTs with Al₂O₃ dielectric layer exhibit high mobility of 7.23?cm² V^?1 s^?1 at the low operating voltage of 3?V, which is much superior to that on SiO₂ dielectrics with mobility of 1.22?cm²/V^?1 s^?1 at the operating voltage of 40?V. These results demonstrate that solution-processed Al₂O₃ thin films are promising for low-power and high-performance oxide devices.     

Hydrogen ion sensing characteristics of Na3BiO4–Bi2O3 mixed oxide nanostructures based EGFET pH sensor

In the present paper, Na₃BiO₄–Bi₂O₃ films have been tested for hydrogen ion sensing. Na₃BiO₄–Bi₂O₃ mixed oxide nanostructures were deposited on the Indium–Tin-Oxide (ITO) coated glass substrate using a low-cost electrodeposition technique at room temperature. The nanostructures have been characterized using FESEM and XPS to study their morphology and composition, respectively. Vertically aligned nanostructures (thickness~90 nm) with well-defined edges were seen in FESEM studies. XPS analysis indicates the presence of Na₃BiO₄ and Bi₂O₃. The crystallinity and the mixed phase of the film were further confirmed by X-ray diffraction study. These nanostructures were explored as a potential candidate for pH sensing using them as a sensing film for Extended-Gate Field-Effect Transistor (EGFET). A sensitivity of 49.63 mV/pH has been observed with good linearity. To the best of our knowledge, for the first time vertically aligned Na₃BiO₄–Bi₂O₃ mixed oxide nanostructures are demonstrated as an EGFET-based (Hydrogen ion) pH sensor.