基于变量决策层的启发式变量选择策略

启发式分支策略是SAT求解器中不可或缺的一部分，直接影响求解器的效率。早期的启发式分支决策需要遍历整个子句数据库，效率比较低。随着独立变量状态衰减和（Variable State Independent Decaying Sum, VSIDS）分支策略的出现，SAT求解器的效率有所提高，但VSIDS策略以及它的延伸策略中变量的增量都只是与变量的冲突次数有关，没有考虑变量的决策层在分支策略中的影响。因此当发生冲突时，如果与冲突有关的变量的得分相同而决策层不同时，对于变量的选择就具有随机性。基于此，本文在阐述变量的决策层的重要性之后在VSIDS策略的基础上，提出一种基于变量决策层的启发式变量选择策略--HSVDL策略。然后通过实例显示HSVDL策略在变量决策阶段选择决策层低的变量的可能性比选择决策层高的变量的可能性要大，而且得分比较小，减少了内存的占用。最后通过实验表明HSVDL策略能够求解出更多的实例，求解器的效率也有所提高，说明该策略有一定的优势。     

FPGA互连测试中的反馈桥接故障覆盖问题

现场可编程门阵列(FPGA)内部资源众多,其中互连资源出现故障的概率远远高于片内其他资源,而在以往许多互连测试研究中,所生成的测试配置存在无法覆盖反馈桥接故障的难题,所以较难有测试配置实现故障列表的100%覆盖。因此通过约束桥接故障只发生在单个查找表(LUT)内的信号线上,并结合单项函数,对反馈桥接故障模型进行优化改进,从根本上解决难题；然后对优化后的反馈桥接故障设置相应的约束条件,再使用布尔可满足性理论(SAT)生成满足约束条件的测试配置。采用优化后的故障模型对ISCAS"89基准电路进行了测试配置生成实验,结果表明生成的测试向量解决了反馈桥接故障的覆盖难题,并且在实现故障列表的100%覆盖下,优化后的故障模型所需要的测试配置数最少。     

Hybrid tabu search and a truncated branch-and-bound for the unrelated parallel machine scheduling problem

We consider the problem of scheduling a number of jobs on a number of unrelated parallel machines in order to minimize the makespan. We develop three heuristic approaches, i.e., a genetic algorithm, a tabu search algorithm and a hybridization of these heuristics with a truncated branch-and-bound procedure. This hybridization is made in order to accelerate the search process to near-optimal solutions. The branch-and-bound procedure will check whether the solutions obtained by the meta-heuristics can be scheduled within a tight upper bound. We compare the performances of these heuristics on a standard dataset available in the literature. Moreover, the influence of the different heuristic parameters is examined as well. The computational experiments reveal that the hybrid heuristics are able to compete with the best known results from the literature.     

基于集对分析的空投师训练装备系统方案优选

为了确定空投师训练系统最佳方案,根据空投师训练需求特点,运用集对分析方法,建立了以训练科目和经济性为基础的空投师训练系统方案优选模型,确定了基于同一度、差异度和对立度的决策系数。最后以实例确定了各种训练设备的适用程度,形成了训练系统最优方案。     

Using working memory theory to investigate the construct validity of multiple-choice reading comprehension tests such as the SAT.

When taking multiple-choice tests of reading comprehension such as the Scholastic Assessment Test (SAT), test takers use a range of strategies that vary in the extent to which they emphasize reading the questions versus reading the passages. Researchers have challenged the construct validity of these tests because test takers can achieve better-than-chance performance even if they do not read the passages at all. By using an individual-differences approach that compares the relative power of working memory span to predict SAT performance for different test-taking strategies, the authors show that the SAT appears to be tapping reading comprehension processes as long as test takers engage in at least some reading of the passages themselves. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

导管数控弯曲自动编程技术研究与系统开发

数控弯管加工是实现导管数字化集成制造的关键环节,数控编程是进行数控弯管的前提。在研究基于导管三维模型的零件信息提取、数控加工参数计算与补偿和数控编程等技术基础上,自行开发面向不同数控系统的导管数控弯曲自动编程系统,并在某新卫星的导管生产中得到了应用。     

时序电路等价验证的触发器匹配

通常的时序电路等价性验证方法是将触发器按时序展开,从而将时序电路转化为组合电路进行验证。而一般在待验证的两个时序电路中,触发器是一一对应的,找到触发器的对应关系,时序电路的验证就会得到很大的简化。该文通过一种新的基于布尔可满足性(SAT)算法的自动测试模式生成(ATPG)匹配模型建立联接电路,使用时序帧展开传递算法比较触发器的帧时序状态输出,同时在SAT解算中加入信息学习继承等启发式算法,将时序电路的触发器一一匹配。在ISCAS89电路上的实验结果表明,该文算法在对触发器的匹配问题上是非常有效的。     

A parsimony tree for the SAT2002 competition

Twenty of the programs (solvers) submitted to the SAT 2002 Contest had no disqualifying errors. These solvers were run on 2023 satisfiability problems of varying hardnesses. Each solver was judged by which problems it could solve within the allowed time limit. Twelve solvers were best on some problem – they could solve it and the others could not. Only two solvers could not beat each remaining solver on some problems (where the problems could vary depending on which solver it was trying to beat). Thus, there is evidence that 18 solvers were extremely good. It is interesting to analyze the contest results in a way that groups together solvers with similar strengths and weaknesses. This paper uses the parsimony algorithm to produce a classification of the twenty solvers. The paper also has a second classification, almost the same as the first, for the twenty solvers, updated versions of two solvers, and a fictitious state of the art solver. The contest problems came in three groups, Industrial, Hand Made, and Random. The Random group of problems was about three times as large as the other two together. The classification identifies four groups of solvers (plus a miscellaneous group): weak solvers, incomplete solvers which are very good at some satisfiable Random problems, complete solvers which are very good at most Random problems, and complete solvers which are very good at Industrial and Hand Made problems.     

Scalable Delay Fault BIST for Use with Low-Cost ATE

We present a BIST architecture based on a Multi-Input Signature Register (MISR) expanding single input vectors into sequences, which are used for testing of delay faults. Input vectors can be stored on-chip or in the ATE; in the latter case, a low speed tester can be employed though the sequences are applied at-speed to the block-under-test. The number of input vectors (and thus the area demand on-chip or ATE memory requirements) can be traded for the test application time.We propose several methods for generating input vectors, which differ in test application time, area requirements and algorithm run-time. As all of them require only a two-pattern test as input, IP cores can be handled by these methods.The block-under-test can be switched off for some amount of time between application of consecutive input vectors. We provide arguments why this approach may be the only way to meet thermal and power constraints. Furthermore, we demonstrate how the BIST scheme can use these cool-down breaks for re-configuration.     

利用改善的静态隐含策略加速等价性验证

随着近年来高效SAT(Satisfiability)求解算法提出，SAT已成为集成电路形式验证方法中重要引擎之一。但在运用SAT验证时需将电路结构转化为成OR-AND两级逻辑描述，丢失了电路的拓扑信息。本文利用改善的静态隐含策略来提取有用子句作为预处理，来加快验证过程。本文算法在原有静态隐含技术的基础上，引入了关联节点隐含及隐含过程加速策略。给出的ISCAS85电路的实验结果表明算法的有效性。