一种用于电流型电化学传感器的CMOS模拟前端芯片

本文提出了一种用于电流型电化学传感器的CMOS模拟前端芯片,芯片具有高度可编程性,其内部集成了可通过I2C接口总线与外部控制芯片通信的可配置数字模块电路。结合incremental型sigma-delta模数转换器与数字域相关双采样技术,提出并实现了一种新的两次采样的系统架构。该芯片基于华虹宏力0.18μm标准CMOS工艺流片,消耗芯片面积为1.3 mm × 1.9 mm,测试结果表明：该芯片16位数字输出具有高精度,高线性度特性,可检测溶液中磷酸根离子浓度的精度为0.01 mg/L。     

一种面向Microsoft Windows的AMBA设备PCI虚拟化机制

PKUnity-86是基于x86处理器和AMBA开放总线架构的系统芯片,既能快速集成各种标准IP核,又支持Microsoft Windows和x86应用程序.如何使AMBA设备支持工业标准的PCI设备枚举和访问,是支持Microsoft Windows 的首要问题.本文提出一种硬件VPCI机制,通过为AMBA设备实现虚...     

Adaptive Online Voltage Scaling Scheme Based on the Nash Bargaining Solution

In an effort to reduce energy consumption, research into adaptive power management in real‐time systems has become widespread. In this paper, a novel dynamic voltage scaling scheme is proposed for multiprocessor systems. Based on the concept of the Nash bargaining solution, a processor's clock speed and supply voltage are dynamically adjusted to satisfy these conflicting performance metrics. In addition, the proposed algorithm is implemented to react adaptively to the current system conditions by using an adaptive online approach. Simulation results clearly indicate that the superior performance of the proposed scheme can strike the appropriate performance balance between contradictory requirements.     

一种基于元操作的宏模块功耗建模方法

为了有效支持系统芯片(SOC)的功耗分析和第三方IP的功耗评估,并有效保护知识产权,提出了元操作的概念,给出了一种基于元操作的宏模块功耗建模方法,建立了元操作功耗模型.该模型是一种周期精确的功耗模型,它描述了宏模块每个时钟周期的动态功耗变化情况.文中论述了这一模型的开发方法和使用方法,并指出,建立元操作功耗模型的关键是模块的功能定义、模块的功能到元操作的映射以及门级功耗样本的产生和收集.通过与门级功耗分析的实验数据对比,此元操作功耗模型的功耗分析误差在4%以内,功耗分析效率可以提高百倍以上.     

Multi-objective two-stage multiprocessor flow shop scheduling – a subgroup particle swarm optimisation approach

Flow shop production system – compared to other economically important production systems – is popular in real manufacturing environments. This study focuses on the flow shop with multiprocessor scheduling problem (FSMP), and develops an improved particle swarm optimisation heuristic to solve it. Additionally, this study designs an integer programming model to perform effectiveness and robustness testing on the proposed heuristic. Experimental results demonstrate a 10% to 50% improvement in the effectiveness of the proposed heuristic in small-scale problem tests, and a 10% to 40% improvement in the robustness of the heuristic in large-scale problem tests, indicating extremely satisfactory performance.     

On an efficient NoC multicasting scheme in support of multiple applications running on irregular sub-networks

When a number of applications simultaneously running on a many-core chip multiprocessor (CMP) chip connected through network-on-chip (NoC), significant amount of on-chip traffic is one-to-many (multicast) in nature. As a matter of fact, when multiple applications are mapped onto an NoC architecture with applicable traffic isolation constraints, the corresponding sub-networks of these applications are mapped onto actually tend to be irregular. In the literature, multicasting for irregular topologies is supported through either multiple unicasting or broadcasting, which, unfortunately, results in overly high power consumption and/or long network latency. To address this problem, a simple, yet efficient hardware-based multicasting scheme is proposed in this paper. First, an irregular oriented multicast strategy is proposed. Literally, following this strategy, an irregular oriented multicast routing algorithm can be designed based on any regular mesh based multicast routing algorithm. One such algorithm, namely, Alternative Recursive Partitioning Multicasting (AL + RPM), is proposed based on RPM, which was designed for regular mesh topology originally. The basic idea of AL + RPM is to find the output directions following the basic RPM algorithm and then decide to replicate the packets to the original output directions or the alternative (AL) output directions based on the shape of the sub-network. The experiment results show that the proposed multicast AL + RPM algorithm can consume, on average, 14% and 20% less power than bLBDR (a broadcasting-based routing algorithm) and the multiple unicast scheme, respectively. In addition, AL + RPM has much lower network latency than the above two approaches. To incorporate AL + RPM into a baseline router to support multicasting, the area overhead is fairly modest, less than 5.5%.     

Low-cost sound-based localization using programmable mixed-signal systems-on-chip

There have been extensive theoretical studies on sound-based localization using both, a pair of microphones and microphone arrays. In contrast, there has been much less work on implementing and experimenting sound-based localization realized as customized electronic designs. This paper presents a low-cost implementation of the sound-based localization method proposed in Halupka et al. [11]. A new method called wave counting is proposed in this paper, as an alternative to the Maximum Likelihood procedure used in [11]. The implementation uses PSoC programmable mixed-signal embedded system-on-chip, which incorporates microcontroller, on-chip SRAM and flash memory, programmable digital blocks, and programmable analog blocks, all integrated on the same chip. The paper presents an extensive set of experiments to characterize the quality of localization using the proposed low-cost design.     

Unified reliability estimation and management of NoC based chip multiprocessors

We present a new architecture level unified reliability evaluation methodology for chip multiprocessors (CMPs). The proposed reliability estimation (REST) is based on a Monte Carlo algorithm. What distinguishes REST from the previous work is that both the computational and communication components are considered in a unified manner to compute the reliability of the CMP. We utilize REST tool to develop a new dynamic reliability management (DRM) scheme to address time-dependent dielectric breakdown and negative-bias temperature instability aging mechanisms in network-on-chip (NoC) based CMPs. Designed as a control loop, the proposed DRM scheme uses an effective neural network based reliability estimation module. The neural-network predictor is trained using the REST tool. We investigate how system’s lifetime changes when the NoC as the communication unit of the CMP is considered or not during the reliability evaluation process and find that differences can be as high as 60%. Full-system based simulations using a customized GEM5 simulator show that reliability can be improved by up to 52% using the proposed DRM scheme in a best-effort scenario with 2–9% performance penalty (using a user set target lifetime of 7 years) over the case when no DRM is employed.     

Locality Aware Optimal Task Scheduling Algorithm for TriBA——A Novel Scalable Architecture

An optimal algorithmic approach to task scheduling for, triplet based architecture（TriBA）, is proposed in this paper. TriBA is considered to be a high performance, distributed parallel computing architecture. TriBA consists of a 2D grid of small, programmable processing units, each physically connected to its three neighbors. In parallel or distributed environment an efficient assignment of tasks to the processing elements is imperative to achieve fast job turnaround time. Moreover, the sojourn time experienced by each individual job should be minimized. The arriving jobs are comprised of parallel applications, each consisting of multiple-independent tasks that must be instantaneously assigned to processor queues, as they arrive. The processors independently and concurrently service these tasks. The key scheduling issues is, when some queue backlogs are small, an incoming job should first spread its tasks to those lightly loaded queues in order to take advantage of the parallel processing gain. Our algorithmic approach achieves optimality in task scheduling by assigning consecutive tasks to a triplet of processors exploiting locality in tasks. The experimental results show that tasks allocation to triplets of processing elements is efficient and optimal. Comparison to well accepted interconnection strategy, 2D mesh, is shown to prove the effectiveness of our algorithmic approach for TriBA. Finally we conclude that TriBA can be an efficient interconnection strategy for computations intensive applications, if tasks assignment is carried out optimally using algorithmic approach.     

基于共享存储器多处理器片上系统的互斥模型*

在原有模型和算法分析的基础上,提出了一种共享存储器MPSOC互斥模型。该模型能适应各种互斥算法的描述、论证需求,能更好地描述任务优先级、实时性;能够适应区分处理器源任务的互斥算法（即区分对待来自不同处理器的任务）;严格区分并发性、并行性,描述更加精确;扩展了服务周期、事件之间关系;能够精确地量化互斥性能指标,以便更好地比较互斥算法优劣。最后,给出了该模型的一个简单实例,对模型应用提供指导。